EL7513
When choosing an inductor, make sure the inductor can
handle the average and peak currents giving by following
formulas (80% efficiency assumed):
ILAVG
=
--I--O------×-----V----O----
0.8 × VIN
(EQ. 2)
ILPK
=
ILAVG
+
1--
2
×
ΔIL
(EQ. 3)
ΔIL = -V----I--NL-----××-----(V--V--O--O----×--–---F-V--S---I--N----)
(EQ. 4)
where:
• ΔIL is the peak-to-peak inductor current ripple in Ampere
• L inductance in µH
• FS switching frequency, typical 1MHz
A wide range of inductance (6.8µH - 68µH) can be used for
the converter to function correctly. For the same series of
inductors, the lower inductance has lower DC resistance
(DCR), which has less conducting loss. But the ripple current
is bigger, which generates more RMS current loss. Figure 11
shows the efficiency of the demo board under different
inductance for a specific series of inductor. For optimal
efficiency in an application, it is a good exercise to check
several adjacent inductance values of your preferred series
of inductors.
For the same inductance, higher overall efficiency can be
obtained by using lower DCR inductor.
EFFICIENCY vs IO
85
VIN = 3.3V FOR
DIFFERENT L
83
L = 33µH
81
L = 22µH
L = 15µH
L = 10µH
79
L = Coilcraft
LPO1704 SERIES
1mm HEIGHT
77
5
10
15
20
25
30
IO (mA)
FIGURE 21. EFFICIENCY OF DIFFERENT INDUCTANCE
(4 LEDs IN A SERIES)
The diode should be Schottky type with minimum reverse
voltage of 20V. The diode's peak current is the same as
inductor's peak current, the average current is IO, and RMS
current is:
IDRMS = ILAVG × IO
(EQ. 5)
Ensure the diode's ratings exceed these current
requirements.
White LED Connections
One leg of LEDs connected in series will ensure the
uniformity of the brightness. 18V maximum voltage enables
4 LEDs can be placed in series.
However, placing LEDs into series/parallel connection can
give higher efficiency as shown in the efficiency curves. One
of the ways to ensure the brightness uniformity is to pre-
screen the LEDs.
PCB Layout Considerations
The layout is very important for the converter to function
properly. Power Ground ( ) and Signal Ground ( ) should
be separated to ensure the high pulse current in the power
ground does not interference with the sensitive signals
connected to Signal Ground. Both grounds should only be
connected at one point right at the chip. The heavy current
paths (VIN-L-LX pin-PGND, and VIN-L-D-C2-PGND) should
be as short as possible.
The trace connected to the CS pin is most important. The
current sense resister R1 should be very close to the pin
When the trace is long, use a small filter capacitor close to
the CS pin.
The heat of the IC is mainly dissipated through the PGND
pin. Maximizing the copper area around the plane is
preferable. In addition, a solid ground plane is always helpful
for the EMI performance.
The demo board is a good example of layout based on the
principle. Please refer to the EL7513 Application Brief for the
layout.
10
FN7112.5
December 22, 2008