FM3104-G 查看數據表（PDF） - Ramtron International Corporation

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FM3104-G

(FM3104 - FM31256) Integrated Processor Companion with Memory

Ramtron International Corporation 

three bytes of a write operation to set the internal

address followed by subsequent read operations.

To perform a selective read, the bus master sends out

the slave address with the LSB set to 0. This specifies

a write operation. According to the write protocol,

the bus master then sends the address bytes that are

loaded into the internal address latch. After the

FM31xx acknowledges the address, the bus master

issues a Start condition. This simultaneously aborts

the write operation and allows the read command to

be issued with the slave address LSB set to a 1. The

operation is now a read from the current address.

Read operations are illustrated below.

RTC/Companion Write Operation

All RTC and Companion writes operate in a similar

manner to memory writes. The distinction is that a

different device ID is used and only one byte address

is needed instead of two. Figure 16 illustrates a single

byte write to this device.

RTC/Companion Read Operation

As with writes, a read operation begins with the

Slave Address. To perform a register read, the bus

FM3104/16/64/256

master supplies a Slave Address with the LSB set to

1. This indicates that a read operation is requested.

After receiving the complete Slave Address, the

FM31xx will begin shifting data out from the current

register address on the next clock. Auto-increment

operates for the special function registers as with the

memory address. A current address read for the

registers look exactly like the memory except that the

device ID is different.

The FM31xx contains two separate address registers,

one for the memory address and the other for the

register address. This allows the contents of one

address register to be modified without affecting the

current address of the other register. For example,

this would allow an interrupted read to the memory

while still providing fast access to an RTC register. A

subsequent memory read will then continue from the

memory address where it previously left off, without

requiring the load of a new memory address.

However, a write sequence always requires an

address to be supplied.

By Master

Start

Address

No

Acknowledge

S

Slave Address 1 A

Data Byte

1P

By FM31xxx

Acknowledge Data

Figure 16. Current Address Memory Read

Stop

By Master

Start

Address

S

Slave Address 1 A

Acknowledge

No

Acknowledge

Data Byte

A

Data Byte

1P

Stop

By FM31xxx

Acknowledge

Data

Figure 17. Sequential Memory Read

Rev. 2.1

Sept. 2011

Page 19 of 26

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