HIP6004ECBZ 查看數據表（PDF） - Intersil

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HIP6004ECBZ

Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor

Intersil 

HIP6004E

TABLE 1. OUTPUT VOLTAGE PROGRAM (Continued)

VID25

mV

0

1

PIN NAME

VID3

1

1

VID2

1

1

VID1

1

1

VID0

1

1

NOMINAL OUTPUT

VOLTAGE DACOUT

1.300

1.325

VID25

mV

0

1

PIN NAME

VID3

0

0

VID2

1

1

VID1

1

1

VID0

1

1

NOMINAL OUTPUT

VOLTAGE DACOUT

1.700

1.725

0

1

1

1

0

1.350

0

0

1

1

0

1.750

1

1

1

1

0

1.375

1

0

1

1

0

1.775

0

1

1

0

1

1.400

0

0

1

0

1

1.800

1

1

1

0

1

1.425

1

0

1

0

1

1.825

NOTE: 0 = connected to GND or VSS, 1 = connected to VDD through pull-up resistors or leave the pins floating. Internal pull-ups will force the floating

VID pins to HIGH.

VIN

HIP6004E

UGATE

PHASE

LGATE

PGND

Q1

LO

VOUT

Q2

D2

CIN CO

RETURN

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

Figure 5 shows the critical power components of the converter.

To minimize the voltage overshoot the interconnecting wires

indicated by heavy lines should be part of ground or power

plane in a printed circuit board. The components shown in

Figure 5 should be located as close together as possible.

Please note that the capacitors CIN and CO each represent

numerous physical capacitors. Locate the HIP6004E within 3

inches of the MOSFETs, Q1 and Q2. The circuit traces for the

MOSFETs’ gate and source connections from the HIP6004E

must be sized to handle up to 1A peak current.

Figure 6 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

current paths on the SS pin and locate the capacitor, CSS

close to the SS pin because the internal current source is

only 10µA. Provide local VCC decoupling between VCC and

GND pins. Locate the capacitor, CBOOT as close as practical

to the BOOT and PHASE pins.

BOOT

D1

CBOOT

PHASE

HIP6004E

SS

VCC +12V

CSS

GND

CVCC

+VIN

Q1 LO

Q2

CO

VOUT

FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(VOUT) is regulated to the Reference voltage level. The

error amplifier (Error Amp) output (VE/A) is compared with

the oscillator (OSC) triangular wave to provide a pulse-

width modulated (PWM) wave with an amplitude of VIN at

the PHASE node.

7

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