HM5116400S-6 查看數據表（PDF） - Hitachi -> Renesas Electronics

零件编号

产品描述 (功能)

生产厂家

HM5116400S-6

4,194,304-word 4-bit Dynamic RAM

Hitachi -> Renesas Electronics 

HM5116400 Series, HM5117400 Series

Notes: 1. AC measurements assume tT = 5 ns.

2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization

cycles (any combination of cycles containing -only refresh or -before- refresh). If

the internal refresh counter is used, a minimum of eight -before- refresh cycles are

required.

3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a

reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is

controlled exclusively by tCAC.

4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a

reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is

controlled exclusively by tAA.

5. Either tOED or tCDD must be satisfied.

6. Either tDZO or tDZC must be satisfied.

7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition

times are measured between VIH (min) and VIL (max).

8. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum

recommended value shown in this table, tRAC exceeds the value shown.

9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.

10. Assumes that tRCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max).

11. Assumes that tRAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max).

12. Either tRCH or tRRH must be satisfied for a read cycles.

13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition

and are not referred to output voltage levels.

14. t , WCS t , RWD t , CWD tAWD and tCPW are not restrictive operating parameters. They are included in the

data sheet as electrical characteristics only; if tWCS tWCS (min), the cycle is an early write cycle

and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD

tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW

tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the

selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out

(at access time) is indeterminate.

15. These parameters are referred to

leading edge in early write cycles and to

edge in delayed write or read-modify-write cycles.

leading

16. tRASP defines

pulse width in Fast page mode cycles.

17. Access time is determined by the longest among tAA, tCAC and t . CPA

18. In delayed write or read-modify-write cycles, must disable output buffer prior to applying data

to the device.

19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M

4 are don’t care during test mode. Test mode is set by performing a -and- -before-

(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1

to I/O4) and read out from each I/O.

If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read

cycle, then the device has passed. If they are not equal, data output pin is a low state, then the

device has failed.

Refresh during test mode operation can be performed by normal read cycles or by WCBR

refresh cycles.

To get out of test mode and enter a normal operation mode, perform either a regular -

before- refresh cycle or -only refresh cycle.

20. In a test mode read cycle, the value of tRAC, tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the

specified value. These parameters should be specified in test mode cycles by adding the above

value to the specified value in this data sheet.

15

Share Link: