HT48RA0-3/HT48CA0-3
Pin Description
Pin Name
I/O
Configuration
Option
Description
PA0~PA7 I/O
¾
Bidirectional 8-bit input/output port with pull-high resistors. Software instructions
determine if the pin is an NMOS output or Schmitt Trigger input.
PB0, PB1 I/O
Wake-up
Bidirectional 2-bit input/output lines with pull-high resistors. Each individual bit
can be configured as a wake-up input by a configuration option. Software in-
structions determine if the pin is an NMOS output or Schmitt Trigger input.
PB2~PB6 I
Wake-up
5-bit Schmitt Trigger input lines with pull-high resistors. Each individual bit can
be configured as a wake-up input by a configuration option.
PB7
I
Wake-up
1-bit Schmitt trigger input lines without pull-high resistor. This bit can be config-
ured as a wake-up input by a configuration option.
REM
O
OSC1
I
VDD
¾
VSS
¾
¾
Carrier output pin.
¾
OSC1 is connected to an external resistor for the internal system clock.
¾
Positive power supply
¾
Negative power supply, ground
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+4.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Symbol
Parameter
VDD
IDD
ISTB
VIL
VIH
VLVR
IOL
IOH
RPH
VPOR
RPOR
Operating Voltage
Operating Current
Standby Current
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Low Voltage Reset Voltage
I/O Ports Sink Current
REM Output Source Current
Pull-high Resistance
VDD Start Voltage to ensure
Power-on Reset
VDD Rise Rate to ensure
Power-on Reset
Test Conditions
VDD
Conditions
Min.
¾
¾
2.0
3V No load, fSYS=4MHz
¾
3V No load, system HALT ¾
3V
¾
0
3V
¾
0.8VDD
¾
¾
1.8
3V VOL=0.1VDD
4
3V VOH=0.9VDD
-5
3V
¾
100
¾
¾
¾
¾
¾
0.035
Typ.
¾
0.7
¾
¾
¾
1.9
8
-7
150
¾
¾
Max.
3.6
1.5
1
0.2VDD
VDD
2.0
¾
¾
200
100
¾
Unit
V
mA
mA
V
V
V
mA
mA
kW
mV
V/ms
Rev.1.10
3
October 12, 2007