ICS553MI 查看數據表（PDF） - Integrated Circuit Systems

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ICS553MI

LOW SKEW 1 TO 4 CLOCK BUFFER

Integrated Circuit Systems 

Pin Assignment

VDD 1

Q0 2

Q1 3

GND 4

8 OE

7 Q3

6 Q2

5 ICLK

8 Pin (150 mil) SOIC

ICS553

LOW SKEW 1 TO 4 CLOCK BUFFER

Pin Descriptions

Pin

Number

1

2

3

4

5

6

7

8

Pin

Name

VDD

Q0

Q1

GND

ICLK

Q2

Q3

OE

Pin

Type

Power

Output

Output

Power

Input

Output

Output

Input

Pin Description

Connect to +2.5V, +3.3V or +5.0V.

Clock Output 0.

Clock Output 1.

Connect to ground.

Clock Input. 5V tolerant input.

Clock Output 2.

Clock Output 3.

Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.

External Components

A minimum number of external components are required for proper operation. A decoupling capacitor of

0.01 µF should be connected between VDD on pin 1 and GND on pin 4, as close to the device as possible.

A 33 Ω series terminating resistor may be used on each clock output if the trace is longer than 1 inch.

To achieve the low output skew that the ICS553 is capable of, careful attention must be paid to board

layout. Essentially, all 4 outputs must have identical terminations, identical loads and identical trace

geometries. If they do not, the output skew will be degraded. For example, using a 30Ω series termination

on one output (with 33Ω on the others) will cause at least 15ps of skew.

MDS 553 H

2

Revision 080404

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com

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