ICS8524AYT(2004) 查看數據表（PDF） - Integrated Circuit Systems

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ICS8524AYT
(Rev.:2004)

LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS8524

LOW SKEW, 1-TO-22

DIFFERENTIAL-TO-HSTL FANOUT BUFFER

TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA=0°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum

IIH

Input High Current PCLK, nPCLK

VDD = VIN = 3.465V

150

IIL

Input Low Current PCLK, nPCLK

VDD = 3.465V, VIN = 0V

-150

VPP

Peak-to-Peak Input Voltage

0.3

1

VCMR

Common Mode Input Voltage; NOTE 1, 2

GND + 1.5

VDD

NOTE 1: Common mode voltage is defined as VIH.

NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.

Units

µA

µA

V

V

TABLE

4E.

HSTL

DC

CHARACTERISTICS,

V

DD

=

3.3V±5%,

V

DDO

=

1.8V±0.2V,

TA=0°C

TO

85°C

Symbol Parameter

Test Conditions

Minimum

V

Output High Voltage; NOTE 1

1.0

OH

VOL

Output Low Voltage; NOTE 1

0

VOX

Output Crossover Voltage; NOTE 2

40

VSWING Peak-to-Peak Output Voltage Swing

0.6

NOTE 1: Outputs terminated with 50Ω to ground.

NOTE 2: Defined with respect to output voltage swing at a given condition.

Typical

Maximum

1.4

0.4

60

1.1

Units

V

V

%

V

TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA=0°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum

fMAX

tPD

tsk(o)

Output Frequency

Propagation Delay; NOTE 1

Output Skew; NOTE 2, 4

500

1.7

2.7

80

tsk(pp) Part-to-Part Skew; NOTE 3, 4

700

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter section

0.04

tR / tF

tS

tH

odc

Output Rise/Fall Time

Setup Time

Hold Time

Output Duty Cycle

20% to 80%

300

700

1.0

0.5

IJ 133MHz

49

51

133 < IJ 266MHz

48

52

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions at the same temperature. Using the same type of inputs on each device,

the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Units

MHz

ns

ps

ps

ps

ps

ns

ns

%

%

8524AY

www.icst.com/products/hiperclocks.html

5

REV. B NOVEMBER 19, 2004

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