IDT79R3051E-25 查看數據表（PDF） - Integrated Device Technology

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IDT79R3051E-25

RISControllers

Integrated Device Technology 

IDT79R3051/79R3052 INTEGRATED RISControllers

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PIN DESCRIPTION

PIN NAME

I/O

A/D(31:0)

I/O

Addr(3:2)

O

Diag(1)

O

Diag(0)

O

ALE

O

DataEn

O

DESCRIPTION

Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction

in one phase, and which is used to transmit data between the CPU and external memory resources during

the rest of the transfer.

Bus transactions on this bus are logically separated into two phases: during the first phase, information

about the transfer is presented to the memory system to be captured using the ALE output. This

information consists of:

Address(31:4):

BE(3:0):

The high-order address for the transfer is presented on A/D(31:4).

These strobes indicate which bytes of the 32-bit bus will be involved in

the transfer, and are represented on A/D(3:0).

During write cycles, the bus contains the data to be stored and is driven from the internal write buffer.

On read cycles, the bus receives the data from the external resource, in either a single data transaction

or in a burst of four words, and places it into the on-chip read buffer.

Low Address (3:2) A 2-bit bus which indicates which word is currently expected by the processor.

Specifically, this two bit bus presents either the address bits for the single word to be transferred (writes

or single datum reads) or functions as a two bit counter starting at ‘00’ for burst read operations.

Diagnostic Pin 1. This output indicates whether the current bus read transaction is due to an on-

chip cache miss, and also presents part of the miss address. The value output on this pin is time

multiplexed:

Cached:

During the phase in which the A/D bus presents address information, this

pin is an active high output which indicates whether the current read is

a result of a cache miss. The value of this pin at this time in other than

read cycles is undefined.

Miss Address (3):

During the remainder of the read operation, this output presents address

bit (3) of the address the processor was attempting to reference when the

cache miss occurred. Regardless of whether a cache miss is being

processed, this pin reports the transfer address during this time.

Diagnostic Pin 0. This output distinguishes cache misses due to instruction references from those due

to data references, and presents the remaining bit of the miss address. The value output on this pin is

also time multiplexed:

I/D:

If the “Cached” Pin indicates a cache miss, then a high on this pin at this

time indicates an instruction reference, and a low indicates a data

reference. If the read is not due to a cache miss but rather an uncached

reference, then this pin is undefined during this phase.

Miss Address (2):

During the remainder of the read operation, this output presents address

bit (2) of the address the processor was attempting to reference when the

cache miss occurred. Regardless of whether a cache miss is being

processed, this pin reports the transfer address during this time.

Address Latch Enable: Used to indicate that the A/D bus contains valid address information for the bus

transaction. This signal is used by external logic to capture the address for the transfer, typically using

transparent latches.

External Data Enable: This signal indicates that the A/D bus is no longer being driven by the processor

during read cycles, and thus the external memory system may enable the drivers of the memory system

onto this bus without having a bus conflict occur. During write cycles, or when no bus transaction is

occurring, this signal is negated, thus disabling the external memory drivers.

2874 tbl 02

5.3

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