IS61LV12824-12B 查看數據表（PDF） - Integrated Silicon Solution

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IS61LV12824-12B

128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

Integrated Silicon Solution 

IS61LV12824

ISSI ®

WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)

Symbol Parameter

-8

-9

-10

-12

Min. Max. Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time

8—

9—

10 —

12 —

ns

tSCE CE1, CE2 to Write End

tSCE2 CE2 to Write End

7—

7—

8—

8—

8

—

8

—

9—

ns

9—

tAW Address Setup Time

to Write End

7—

8—

8

—

9—

ns

tHA Address Hold from Write End 0 —

0—

0

—

0—

ns

tSA Address Setup Time

0—

0—

0

—

0—

ns

tPWE1 WE Pulse Width (OE = HIGH) 6 —

8—

8

—

9—

ns

tPWE2 WE Pulse Width (OE = LOW) 6 —

9—

9

—

10 —

ns

tSD Data Setup to Write End

4.5 —

5—

5

—

5—

ns

tHD Data Hold from Write End 0 —

0—

0

—

0—

ns

tHZWE(2) WE LOW to High-Z Output — 3.5

— 3.5

— 3.5

— 3.5

ns

tLZWE(2) WE HIGH to Low-Z Output 3 —

3—

3

—

3—

ns

Notes:

1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE1, CE2 LOW, CE2 HIGH and WE LOW. All signals must be in valid

states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are

referenced to the rising or falling edge of the signal that terminates the write.

8

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY Rev. B

12/15/99

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