ISL6173DRZA-T(2005) 查看數據表（PDF） - Intersil

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ISL6173DRZA-T
(Rev.:2005)

Dual Low Voltage Hot Swap Controller

Intersil 

IC Operation State Diagram

ISL6173

No

Pow er

Apply Pow er

Bias>1V

PG

&

FLT

Outputs

Valid

Bias>2V

FLT

Cleared

EN De-asserted

Gate

Pulldow n

Io>>ICR

(WOC)

Output

Voltage

Available

Io>ICR

Vuv<633mV Vuv>645mV

PG

Asserted

EN Asserted

Soft Start

(Tss)

Run

OC Timer

(Toc)

Io>ICR

Current

Limit

Mode

Io>=Icr

AND

t>Toc

Count 64

Pulses

&

Reset

RTR/LTCH = L

FLT

Asserted

Reset &

Latch

Off

State

RTR/LTCH = H

FIGURE 16.

12

FN9186.2

February 15, 2005

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