ISL6236AIRZ-T 查看數據表（PDF） - Intersil

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ISL6236AIRZ-T

High-Efficiency, Quad-Output, Main Power Supply Controllers for Notebook Computers

Intersil 

ISL6236A

Pin Descriptions

PIN

NAME

FUNCTION

1

REF 2V Reference Output. Bypass to GND with a 0.1µF (min) capacitor. REF can source up to 50A for external loads.

Loading REF degrades FB and output accuracy according to the REF load-regulation error.

2

TON Frequency Select Input. Connect to GND for 400kHz/500kHz operation. Connect to REF (or leave OPEN) for

400kHz/300kHz operation. Connect to VCC for 200kHz/300kHz operation (5V/3.3V SMPS switching frequencies,

respectively.)

3

VCC Analog Supply Voltage Input for PWM Core. Bypass to GND with a 1µF ceramic capacitor.

4

EN LDO LDO Enable Input. The LDO is enabled if EN LDO is within logic high level and disabled if EN LDO is less than the logic

low level.

5

VREF3 3.3V Reference Output. VREF3 can source up to 5mA for external loads. Bypass to GND with a 0.01µF capacitor if

loaded. Leave open if there is no load.

6

VIN Power-Supply Input. VIN is used for the constant-on-time PWM on-time one-shot circuits. VIN is also used to power the

linear regulators. The linear regulators are powered by SMPS1 if OUT1 is set greater than 4.78V and BYP is tied to

OUT1. Connect VIN to the battery input and bypass with a 1µF capacitor.

7

LDO Linear-Regulator Output. LDO can provide a total of 100mA external loads. The LDO regulates at 5V If LDOREFIN is

connected to GND. When the LDO is set at 5V and BYP is within 5V switchover threshold, the internal regulator shuts

down and the LDO output pin connects to BYP through a 0.7Ω switch. The LDO regulates at 3.3V if LDOREFIN is

connected to VCC. When the LDO is set at 3.3V and BYP is within 3.3V switchover threshold, the internal regulator

shuts down and the LDO output pin connects to BYP through a 1.5Ω switch. Bypass LDO output with a minimum of

4.7µF ceramic.

8

LDOREFIN LDO Reference Input. Connect LDOREFIN to GND for fixed 5V operation. Connect LDOREFIN to VCC for fixed 3.3V

operation. LDOREFIN can be used to program LDO output voltage from 0.7V to 4.5V. LDO output is two times the

voltage of LDOREFIN. There is no switchover in adjustable mode.

9

BYP BYP is the switchover source voltage for the LDO when LDOREFIN is connected to GND or VCC. Connect BYP to 5V

if LDOREFIN is tied to GND. Connect BYP to 3.3V if LDOREFIN is tied to VCC.

10

OUT1 SMPS1 Output Voltage-Sense Input. Connect to the SMPS1 output. OUT1 is an input to the Constant on-time-PWM

on-time one-shot circuit. It also serves as the SMPS1 feedback input in fixed-voltage mode.

11

FB1 SMPS1 Feedback Input. Connect FB1 to GND for fixed 5V operation. Connect FB1 to VCC for fixed 1.5V operation

Connect FB1 to a resistive voltage-divider from OUT1 to GND to adjust the output from 0.7V to 5.5V.

12

ILIM1 SMPS1 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM1 over a

0.2V to 2V range. There is an internal 5µA current source from VCC to ILIM1. Connect ILIM1 to REF for a fixed 200mV

threshold. The logic current limit threshold is default to 100mV value if ILIM1 is higher than VCC - 1V.

13

POK1 SMPS1 Power-Good Open-Drain Output. POK1 is low when the SMPS1 output voltage is more than 10% below the

normal regulation point or during soft-start. POK1 is high impedance when the output is in regulation and the soft-start

circuit has terminated. POK1 is low in shutdown.

14

EN1 SMPS1 Enable Input. The SMPS1 is enabled if EN1 is greater than the logic high level and disabled if EN1 is less than

the logic low level. If EN1 is connected to REF, the SMPS1 starts after the SMPS2 reaches regulation (delay start). Drive

EN1 below 0.8V to clear fault level and reset the fault latches.

15

UGATE1 High-Side MOSFET Floating Gate-Driver Output for SMPS1. UGATE1 swings between PHASE1 and BOOT1.

16

PHASE1 Inductor Connection for SMPS1. PHASE1 is the internal lower supply rail for the UGATE1 high-side gate driver.

PHASE1 is the current-sense input for the SMPS1.

17

BOOT1 Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor according to the “Typical Application

Circuits” on page 19 (Figure 66, Figure 67, and Figure 69). See “MOSFET Gate Drivers (UGATE, LGATE )” on page 29.

18

LGATE1 SMPS1 Synchronous-Rectifier Gate-Drive Output. LGATE1 swings between GND and PVCC.

19

PVCC PVCC is the supply voltage for the low-side MOSFET driver LGATE. Connect a 5V power source to the PVCC pin

(bypass with 1µF MLCC capacitor to PGND if necessary). There is internal 10Ω connecting PVCC to VCC. Make sure

that both VCC and PVCC are bypassed with 1µF MLCC capacitors.

20

SECFB The SECFB is used to monitor the optional external 14V charge pump. Connect a resistive voltage-divider from 14V

charge pump output to GND to detect the output. If SECFB drops below the threshold voltage, LGATE1 turns on for

300ns. This will refresh the external charge pump driven by LGATE1 without over-discharging the output voltage.

21

GND Analog Ground for both SMPS and LDO. Connect externally to the underside of the exposed pad.

7

FN6453.0

March 14, 2007

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