ISL6422ERZ-T 查看數據表（PDF） - Intersil

零件编号

产品描述 (功能)

生产厂家

ISL6422ERZ-T

Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs

Intersil 

ISL6422

Data Validity

The data on the SDA line must be stable during the HIGH

period of the clock. The HIGH or LOW state of the data line

can change only when the clock signal on the SCL line is

LOW. Refer to Figure 4.

SDA

SCL

DATA LINE CHANGE

STABLE OF DATA

DATA VALID ALLOWED

FIGURE 4. DATA VALIDITY

START and STOP Conditions

As shown in Figure 5, the START condition is a HIGH to

LOW transition of the SDA line while SCL is HIGH.

The STOP condition is a LOW to HIGH transition on the SDA

line while SCL is HIGH. A STOP condition must be sent

before each START condition.

SDA

SCL

S

P

START

CONDITION

STOP

CONDITION

FIGURE 5. START AND STOP WAVEFORMS

Byte Format

Every byte put on the SDA line must be eight bits long. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte has to be followed by an

acknowledge bit. Data is transferred with the most significant

bit first (MSB).

Acknowledge

The master (microprocessor) puts a resistive HIGH level on

the SDA line during the acknowledge clock pulse (see

Figure 6). The peripheral that acknowledges has to pull

down (LOW) the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during this clock

pulse. (Set-up and hold times must also be taken into

account.)

The peripheral which has been addressed has to generate

an acknowledge after the reception of each byte, otherwise

the SDA line remains at the HIGH level during the ninth

clock pulse time. In this case, the master transmitter can

generate the STOP information in order to abort the transfer.

The ISL6422 will not generate the acknowledge if the

POWER OK signal from the UVLO is LOW.

SCL

1

2

8

9

SDA

START

MSB

ACKNOWLEDGE

FROM SLAVE

FIGURE 6. ACKNOWLEDGE ON THE I2C BUS

Transmission Without Acknowledge

Avoiding detection of the acknowledgement, the

microprocessor can use a simpler transmission; it waits one

clock pulse without checking the slave acknowledging and

sends the new data.

This approach, though, is less protected from error and

decreases the noise immunity.

ISL6422 Software Description

Interface Protocol

The interface protocol is comprised of the following, as

shown in Table 2:

• Start condition (S)

• Chip address byte (MSB on left; the LSB bit determines

read (1) or write (0) transmission) (the assigned I2C slave

address for the ISL6422 is 0001 00XX)

• Sequence of data (1 byte + Acknowledge)

• Stop condition (P)

TABLE 2. INTERFACE PROTOCOL

S 0 0 0 1 0 0 0 R/W ACK Data (8 bits) ACK P

System Register Format

• R, W = Read and Write bit

• R = Read-only bit

• X = Unused

All bits reset to 0 at Power-On

TABLE 3. STATUS REGISTER 1 (SR1)

R, W R, W R, W R

R

R

R

R

SR1H SR1M SR1L OTF CABF1 OUVF1 OLF1 BCF1

TABLE 4. TONE REGISTER 2 (SR2)

R, W R, W R, W R, W R, W R, W R, W

SR2H SR2M SR2L ENT1 MSEL1 TTH1 X

R, W

X

TABLE 5. COMMAND REGISTER 3 (SR3)

R, W R, W R, W R, W R, W R, W R, W R, W

SR3H SR3M SR3L DCL1 VSPEN1 ISEL1R ISEL1H ISEL1L

X

12

FN9190.1

April 10, 2007

Share Link: