ISL90843UIU1027Z 查看數據表（PDF） - Intersil

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ISL90843UIU1027Z

Low Noise, Low Power, I2C® Bus, 256 Taps

Intersil 

ISL90843

bus as a transmitter and the receiving device as the receiver.

The device controlling the transfer is a master and the

device being controlled is the slave. The master always

initiates data transfers and provides the clock for both

transmit and receive operations. Therefore, the ISL90843

operates as a slave device in all applications.

All communication over the I2C interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (See

Figure 11). On power-up of the ISL90843 the SDA pin is in

the input mode.

All I2C interface operations must begin with a START

condition, which is a HIGH to LOW transition of SDA while

SCL is HIGH. The ISL90843 continuously monitors the SDA

and SCL lines for the START condition and does not

respond to any command until this condition is met (See

Figure 11). A START condition is ignored during the power-

up of the device.

All I2C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while

SCL is HIGH (See Figure 11). A STOP condition at the end

of a read operation, or at the end of a write operation places

the device in its standby mode.

An ACK, Acknowledge, is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after

transmitting eight bits. During the ninth clock cycle, the

receiver pulls the SDA line LOW to acknowledge the

reception of the eight bits of data (See Figure 12).

The ISL90843 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL90843 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation

A valid Identification Byte contains 01010 as the five MSBs,

and the following two bits matching the logic values present

at pins A1 and A0. The LSB is in the Read/Write bit. Its value

is “1” for a Read operation, and “0” for a Write operation

(See Table 1).

TABLE 1. IDENTIFICATION BYTE FORMAT

Logic values at pins A1, and A0 respectively

0

1

0

1

0

A1 A0 R/W

(MSB)

(LSB)

SCL

SDA

START

DATA

DATA

DATA

STABLE CHANGE STABLE

STOP

FIGURE 11. VALID DATA CHANGES, START, AND STOP CONDITIONS

SCL FROM

MASTER

1

SDA OUTPUT FROM

TRANSMITTER

8

9

HIGH IMPEDANCE

SDA OUTPUT FROM

RECEIVER

HIGH IMPEDANCE

START

ACK

FIGURE 12. ACKNOWLEDGE RESPONSE FROM RECEIVER

8

FN8095.2

March 29, 2006

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