ISP1183BS 查看數據表（PDF） - Philips Electronics

零件编号

产品描述 (功能)

生产厂家

ISP1183BS

Low-power Universal Serial Bus interface device with DMA

Philips Electronics 

Philips Semiconductors

ISP1183

Low-power USB interface device with DMA

The following example shows the steps that occur in a typical DMA transfer:

1. The ISP1183 receives a data packet in one of its endpoint FIFOs; the packet

must be transferred to memory address 1234H.

2. The ISP1183 asserts the DREQ signal requesting the 8237 for a DMA transfer.

3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.

4. After completing the current instruction cycle, the CPU places the bus control

signals (MEMR_N, MEMW_N, IOR_N and IOW_N) and the address lines in

three-state and asserts HLDA to inform the 8237 that it has control of the bus.

5. The 8237 sets its address lines to 1234H and activates the MEMW_N and IOR_N

control signals.

6. The 8237 asserts DACK_N to inform the ISP1183 that it will start a DMA transfer.

7. The ISP1183 places the byte or word to be transferred on the data bus lines

because its RD_N signal was asserted by the 8237.

8. The 8237 waits one DMA clock period and then deasserts MEMW_N and

IOR_N. This latches and stores the byte or word at the desired memory location.

It also informs the ISP1183 that the data on the bus lines has been transferred.

9. The ISP1183 deasserts the DREQ signal to indicate to the 8237 that DMA is no

longer needed. In the single cycle mode this is done after each byte or word, in

the burst mode following the last transferred byte or word of the DMA cycle.

10. The 8237 deasserts the DACK_N output indicating that the ISP1183 must stop

placing data on the bus.

11. The 8237 places the bus control signals (MEMR_N, MEMW_N, IOR_N and

IOW_N) and the address lines in three-state and deasserts the HRQ signal,

informing the CPU that it has released the bus.

12. The CPU acknowledges control of the bus by deasserting HLDA. After activating

the bus control lines (MEMR_N, MEMW_N, IOR_N and IOW_N) and the address

lines, the CPU resumes the execution of instructions.

For a typical bulk transfer, the above process is repeated 64 times, once for each

byte. After each byte, the address register in the DMA controller is incremented and

the byte counter is decremented.

11.3 DACK-only mode

The DACK-only DMA mode is selected by setting bit DAKOLY in the Hardware

Configuration register (see Table 20). The pin functions for this mode are shown in

Table 9. A typical example of the ISP1183 in the DACK-only DMA mode is given in

Figure 10.

Table 9:

Symbol

DREQ

DACK

DACK-only mode: pin functions

Description

I/O

DMA request

O

DMA acknowledge

I

RD_N

read strobe

I

WR_N

write strobe

I

Function

ISP1183 requests a DMA transfer

DMA controller confirms the transfer;

also functions as data strobe

not used

not used

9397 750 11804

Product data

Rev. 01 — 24 February 2004

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

19 of 62

Share Link: