LC72121V(1998) 查看數據表（PDF） - SANYO -> Panasonic

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LC72121V
(Rev.:1998)

PLL Frequency Synthesizers for Electronic Tuning

SANYO -> Panasonic 

LC72121, 72121M, 72121V

Unlocked State Detection Timing

• Unlocked state detection timing

Unlocked state detection is performed during the reference frequency (fref) period (interval). This means that a period

at least as long as the period of the reference frequency is required to recognize the locked/unlocked state. However,

applications must wait at least twice the period of the reference frequency immediately after changing the divisor (N)

before checking the locked/unlocked state.

Figure 1 Unlocked State Detection Timing

For example, if fref is 1 kHz (a period of 1 ms) applications must wait at least 2 ms after the divisor N is changed

before performing a locked/unlocked check.

Figure 2 Circuit Structure

No. 5815-17/22

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