LPC1778FET180(2011) 查看數據表（PDF） - NXP Semiconductors.

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LPC1778FET180
(Rev.:2011)

32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC

NXP Semiconductors. 

NXP Semiconductors

5. Block diagram

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

debug

port

JTAG

interface

EMC

LCD(1)

slave

slave

TEST/DEBUG

INTERFACE

ARM

CORTEX-M3

I-code D-code

bus

bus

LPC178x/7x

GPDMA

CONTROLLER

ETHERNET(1)

USB

DEVICE/

HOST(1)/OTG(1)

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

system

bus

master

master

master

clocks and

controls

slave

ROM

slave

MULTILAYER AHB MATRIX

SRAM

96/80/40 kB

slave

slave

slave

slave

HIGH-SPEED

GPIO

CRC

APB slave group 0

AHB TO

APB

BRIDGE 0

AHB TO

APB

BRIDGE 1

SSP1

UART0/1

slave

FLASH

ACCELERATOR

FLASH

512/256/128/64 kB

4032 B/

2016 B

EEPROM

APB slave group 1

SSP0/2

I2C0/1

CAN 0/1

TIMER 0/1

WINDOWED WDT

UART2/3

USART4(1)

I2C2

SD/MMC(1)

PWM0/1

12-bit ADC

TIMER2/3

QUADRATURE ENCODER(1)

PIN CONNECT

GPIO INTERRUPT CONTROL

DAC

I2S

EVENT RECORDER

MOTOR CONTROL PWM

32 kHz

OSCILLATOR

RTC

SYSTEM CONTROL

BACKUP REGISTERS

RTC POWER DOMAIN

= connected to GPDMA

002aaf528

(1) Not available on all parts. See Table 2.

Fig 1. Block diagram

LPC178X_7X

Objective data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 27 May 2011

© NXP B.V. 2011. All rights reserved.

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