LTC1291 查看數據表（PDF） - Linear Technology
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LTC1291 Datasheet PDF : 20 Pages
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LTC1291
APPLICATI S I FOR ATIO
LABEL MNEMONIC
LDAA
WAIT1 BPL
LDAA
STAA
WAIT2 LDAA
BPL
LDAA
STAA
LDAA
OPERAND
$1029
WAIT1
$51
$102A
$1029
WAIT2
$102A
$62
$52
COMMENTS
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOAD DIN INTO ACC A FROM $51
LOAD DIN INTO SPI, START SCK
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOAD LTC1291 MSBs INTO ACC A
STORE MSBs IN $62
LOAD DUMMY DIN INTO ACC A
FROM $52
LABEL MNEMONIC
STAA
WAIT3 LDAA
BPL
BSET
LDAA
STAA
OPERAND
$102A
$1029
WAIT3
$08,X#$01
$102A
$63
COMMENTS
LOAD DUMMY DIN INTO SPI,
START SCK
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
D0 GOES HIGH (CS GOES HIGH)
LOAD LTC1291 LSBs IN ACC
STORE LSBs IN $63
JMP
LOOP
START NEXT CONVERSION
Interfacing to the Parallel Port of the Intel 8051 Family
The Intel 8051 has been chosen to show the interface
between the LTC1291 and parallel port microprocessors.
Usually the signals CS, DIN and CLK are generated on three
port lines and the DOUT signal is read on a fourth port line.
This works very well. One can save a line by tying the DIN
and DOUT lines together. The 8051 first sends the start bit
and MUX Address to the LTC1291 over the line connected
to P1.2. Then P1.2 is reconfigured as an input and the 8051
reads back the 12-bit A/D result over the same data line.
Timing Diagram for Interface to Intel 8051
PS BIT LATCHED
CS
INTO LTC1291
1
2
3
4
5
CLK
DATA
(DIN/DOUT)
ODD/
START SIGN
SGL/
DIFF MSBF PS
8051 P1.2 OUTPUT DATA
TO LTC1291
8051 P1.2 RECONFIGURED
AS INPUT AFTER THE 5TH RISING
CLK BEFORE THE 5TH FALLING CLK
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
LTC1291 SENDS A/D RESULT
BACK TO 8051 P1.2
LTC1291 TAKES CONTROL OF DATA
LINE ON 5TH FALLING CLK
LTC1291 AI08
Hardware and Software Interface to Intel 8051
DOUT FROM LTC1291 STORED IN 8051 RAM
MSB
R2 B11 B10 B9 B8 B7 B6 B5 B4
LSB
R1 B3 B2 B1 B0 0
0
0
0
ANALOG
INPUTS
CH0
CS
P1.4
CLK
LTC1291
DOUT
P1.3
8051
P1.2
CH1
DIN
MUX ADDRESS
A/D RESULT
LTC1291 AI09
12
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