LTC4359 查看數據表（PDF） - Linear Technology

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LTC4359

Ideal Diode Controller with Reverse Input Protection

Linear Technology 

Applications Information

ON OFF

LTC4359

SHDN

VSS

VN2222LL

1k

4359 F03a

Figure 3a. SHDN Control

OFF ON

48V

240k

2N5551

240k

100k

2N5401

IN

LTC4359

SHDN

100k

VSS

4359 F03b

1k

Figure 3b. Transistor SHDN Control

ON OFF

2k

MOC

207M

48V

1MΩ

IN

SHDN

2MΩ

LTC4359

VSS

4359 F03c

1k

Figure 3c. Opto-Isolator SHDN Control

LTC4359

Input Short Circuit Faults

The dynamic behavior of an active, ideal diode entering

reverse bias is most accurately characterized by a delay

followed by a period of reverse recovery. During the delay

phase some reverse current is built up, limited by parasitic

resistances and inductances. During the reverse recovery

phase, energy stored in the parasitic inductances is trans-

ferred to other elements in the circuit. Current slew rates

during reverse recovery may reach 100A/µs or higher.

High slew rates coupled with parasitic inductances in

series with the input and output paths may cause poten-

tially destructive transients to appear at the IN, SOURCE

and OUT pins of the LTC4359 during reverse recovery.

A zero impedance short circuit directly across the input

and ground is especially troublesome because it permits

the highest possible reverse current to build up during

the delay phase. When the MOSFET finally commutates

the reverse current the LTC4359 IN and SOURCE pins

experience a negative voltage spike, while the OUT pin

spikes in the positive direction.

To prevent damage to the LTC4359 under conditions

of input short circuit, protect the IN, SOURCE and OUT

pins as shown in Figure 4 . The IN and SOURCE pins are

protected by clamping to the VSS pin with two TransZorbs

or TVS. For input voltages 24V and greater, D4 is needed

to protect the MOSFET’s gate oxide during input short

circuit conditions. Negative spikes, seen after the MOSFET

turns off during an input short, are clamped by D2, a 24V

TVS. D2 allows reverse inputs to 24V while keeping the

MOSFET off and is not required if reverse input protection

INPUT PARASITIC

INDUCTANCE

+

–

VIN

REVERSE RECOVERY CURRENT

Q1

FDMS86101

INPUT

SHORT

D4

DDZ9699T

12V

D1

SMAT70A

70V

IN SOURCE GATE OUT

D2

SHDN

LTC4359

SMAJ24A

VSS

24V

R1

1k

OUTPUT PARASITIC

INDUCTANCE

+

–

VOUT

CLOAD

COUT

≥1.5µF

4359 F04

Figure 4. Reverse Recovery Produces Inductive Spikes at the IN, SOURCE and OUT Pins.

The Polarity of Step Recovery is Shown Across Parasitic Inductances

4359f

9

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