M30833FJGP 查看數據表（PDF） - MITSUBISHI ELECTRIC

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M30833FJGP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

Rev.B2 DUdenedvseercloprmipenttion for proof reading

Mitsubishi Microcomputers

M32C/83 group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.1.10. Pin description (2/4)

Port

Function

Pin name

I/O type

Description

P5 I/O port

P50 to P57

I/O This is an 8-bit I/O port equivalent to P0.

Clock output

CLKOUT

I/O P53 in this port outputs a divide-by-8 or divide-by-32 clock of

XIN or a clock of the same frequency as XCIN.

Bus control

WRL / WR,

WRH / BHE,

RD

BCLK,

HOLD,

HLDA

ALE,

RDY

O Output WRL, WRH and RD, or WR, BHE and RD bus control

O signals.

O

WRL, WRH, and RD selected

In 16-bit data bus, data is written to even addresses when the

WRL signal is “L”.

Data is written to odd addresses when the WRH signal is “L”.

Data is read when RD is “L”.

WR, BHE, and RD selected

Data is written when WR is “L”.

Data is read when RD is “L”.

Odd addresses are accessed when BHE is “L”. Even

addresses are accessed when BHE is “H”.

Use WR, BHE, and RD when all external memory is an 8-bit

data bus.

O Output operation clock for CPU.

I While the input level at the HOLD pin is “L”, the microcomputer

is placed in the hold state.

O While in the hold state, HLDA outputs a “L” level.

O ALE is used to latch the address.

I While the input level of the RDY pin is “L”, the microcomputer

is in the ready state.

Bus control for DRAM

DW,

CASL,

CASH,

RAS

O When DW signal is “L”, write to DRAM.

O Timing signal when latching to line address of even address.

O Timing signal when latching to line address of odd address.

O Timing signal when latching to row address.

P6 I/O port

P60 to P67

I/O This is an 8-bit I/O port equivalent to P0.

UART port

Intelligent I/O port

P7 I/O port

CTS/RTS/SS

CLK

I/O P60 to P63 are I/O ports for UART0.

P64 to P67 are I/O ports for UART1.

RxD/SCL/STxD

TxD/SDA/SRxD

OUTC/ISCLK

I/O ISCLK is a clock I/O port for intelligent I/O communication.

OUTC is an output port for waveform generation function.

P70 to P77

I/O This is an 8-bit I/O port equivalent to P0.

However, P70 and P71 are N-channel open drain outputs.

Timer A port

Timer B port

TAOUT

TAIN

TBIN

O P70 to P77 are I/O ports for timers A0–A3.

I

I P71 is an input port for timer B5.

Three phase motor

control output port

UART port

Intelligent I/O port

CANOUT

CANIN

V, V

W, W

O P72 and P73 are V phase outputs.

P74 and P75 are W phase outputs.

CTS/RTS/SS

I/O

CLK

RxD/SCL/STxD

TxD/SDA/SRxD

P70 to P73 are I/O ports for UART2.

INPC/OUTC

ISCLK/ISTxD/

ISRxD

IEOUT/IEIN

BEOUT/BEIN

CAN

I/O INPC is an input port for time measurement function.

OUTC is an output port for waveform generation function.

ISCLK is a clock I/O port for intelligent I/O communication.

ISTxD/IEOUT/BEOUT is transmit data output port for intelligent

I/O communication.

ISRxD/IEIN/BEIN is receive data input port for intelligent I/O

communication.

O P76 and P77 are I/O ports for CAN communication function.

I

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