M54HC137D1 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

M54HC137D1

RAD-HARD 3 TO 8 LINE DECODER/LATCH (INVERTING)

STMicroelectronics 

M54HC137

RAD-HARD 3 TO 8 LINE DECODER/LATCH (INVERTING)

s HIGH SPEED:

tPD =18ns (TYP.) at VCC = 6V

s LOW POWER DISSIPATION:

ICC = 2µA (MAX.) at TA=25°C

s HIGH NOISE IMMUNITY:

VNIH = VNIL = 28% VCC (MIN.)

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 4mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s WIDE OPERATING VOLTAGE RANGE:

VCC (OPR) = 2V to 6V

s PIN AND FUNCTION COMPATIBLE WITH

54 SERIES 137

s SPACE GRADE-1: ESA SCC QUALIFIED

s 50 krad QUALIFIED, 100 krad AVAILABLE ON

REQUEST

s NO SEL UNDER HIGH LET HEAVY IONS

IRRADIATION

s DEVICE FULLY COMPLIANT WITH

SCC-9205-013

DESCRIPTION

The M54HC137 is an high speed CMOS 3 TO 8

LINE DECODER/LATCH (INVERTING) fabricated

with silicon gate C2MOS technology.

This device is a 3 to 8 line decoder with latches on

the three address inputs. When GL goes from low

DILC-16

FPC-16

ORDER CODES

PACKAGE

FM

DILC

FPC

M54HC137D

M54HC137K

EM

M54HC137D1

M54HC137K1

to high, the addresses present at the select inputs

(A, B, and C) is stored in the latches. As long as

GL remains high no address changes will be

recognized. Output enable pins G1 and G2,

control the state of the outputs independently of

the select or latch-enable inputs. All the outputs

are high unless G1 is high and G2 is low. The

54HC137 is ideally suited for the implementation

of glitch-free decoders in stored-address

application in bus oriented systems.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION

March 2004

1/10

Share Link: