Philips Semiconductors
5V high-speed universal PLD device
with live insertion capability
Product specification
ABT22V10A5, A7
OUTPUT MACRO CELL
AR
DQ
CLK
Q
SP
0
1
10
11
00
01
S1
S0
S1
S0
OUTPUT CONFIGURATION
0
0
Registered/Active-LOW
0
1
Registered/Active-HIGH
F
1
0
Combinatorial/Active-LOW
1
1
Combinatorial/Active-HIGH
0 = Unprogrammed fuse
1 = Programmed fuse
Figure 2. Output Macro Cell Logic Diagram
SP00375
AR
DQ
CLK
Q
SP
S0 = 0
S1 = 0
F
S0 = 0
S1 = 1
F
a. Registered/Active-LOW
AR
DQ
CLK
Q
SP
S0 = 1
S1 = 0
F
c. Combinatorial/Active-LOW
S0 = 1
S1 = 1
F
b. Registered/Active-HIGH
d. Combinatorial/Active-HIGH
Figure 3. Output Macro Cell Configurations
SP00376
Registered Output Configuration
Each Macro Cell of the ABT22V10A includes a D-type flip-flop for
data storage and synchronization. The flip-flop is loaded on the
LOW-to-HIGH transition of the clock input. In the registered
configuration (S1 = 0), the array feedback is from Q of the flip-flop.
Combinatorial I/O Configuration
Any Macro Cell can be configured as combinatorial by selecting the
multiplexer path that bypasses the flip-flop (S1 = 1). In the
combinatorial configuration, the feedback is from the pin.
Variable Input/Output Pin Ratio
The ABT22V10A has twelve dedicated input lines, and each Macro
Cell output can be an I/O pin. Buffers for device inputs have
complementary outputs to provide user-programmable input signal
polarity.
1996 Dec 16
10