Dual-Output (+ and -) DC-DC
Converters for CCD
VBATT
(2.7V ~ 5V)
FAULT
VINV
R3
187kΩ
1%
R4
30.9kΩ
1%
C5
0.1µF
VBATT
R5
100kΩ
C6
0.22µF
VBST
13
1
VCC
ONBST
9 ONINV
2 FBN
C4
4.7µF
14
LXN
L2
4.7µH
REF
3 AVCC
4
REF
MAX8614A
MAX8614B
6 FLT
PVP 12
L1
2.2µH
LXP 10
D2
CMHSH5-21
VINV
C2 -7.5V AT 100mA
4.7µF
C3
1µF
D1
CMHSH5-21
VBST
C1 +15V AT 50mA
2.2µF
R1
1.4MΩ
1%
R2
100kΩ
1%
7
FBP
GND PGND
5
11
SEQ 8
Figure 1. Typical Application Circuit
It is important to connect the GND pin, the input
bypass-capacitor ground lead, and the output filter
capacitor ground lead to a single point (star ground
configuration) to minimize ground noise and improve
regulation. Also, minimize lead lengths to reduce stray
capacitance, trace resistance, and radiated noise, with
preference given to the feedback circuit, the ground
circuit, and LX_. Place feedback resistors R1–R4 as
close to their respective feedback pins as possible.
Place the input bypass capacitor as close as possible
to AVCC and GND.
Chip Information
PROCESS: BiCMOS
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