MB15E06SR 查看數據表（PDF） - Fujitsu
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MB15E06SR Datasheet PDF : 25 Pages
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MB15E06SR
s PIN DESCRIPTIONS
Pin no.
TSSOP BCC
Pin
name
I/O
1
16
OSCIN
I
2
1
OSCOUT
O
3
2
VP
–
4
3
VCC
–
5
4
DO
O
6
5
GND
–
7
6
Xfin
I
8
7
fin
I
9
8
Clock
I
10
9
Data
I
11
10
LE
I
12
11
PS
I
13
12
N.C.
–
14
13 LD/fout O
15
14
N.C.
–
16
15
N.C.
–
Descriptions
Programmable reference divider input. Connection to a TCXO.
Oscillator output.
Power supply voltage input for the charge pump.
Power supply voltage input.
Charge pump output.
Phase of the charge pump can be selected via programming of the FC bit.
Ground.
Prescaler complementary input, which should be grounded via a capacitor.
Prescaler input.
Connection to an external VCO should be done via AC coupling.
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock.
(Open is prohibited.)
Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
Load enable signal input. (Open is prohibited.)
When LE is set high, the data in the shift register is transferred to a latch
according to the control bit in the serial data.
Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
PS = “H”; Normal mode
PS = “L”; Power saving mode
No connection.
Lock detect signal output (LD)/phase comparator monitoring output (fout).
The output signal is selected via programming of the LDS bit.
LDS = “H”; outputs fout (fr/fp monitoring output)
LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.)
No connection.
No connection.
3
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