MB15F76UL(2001) 查看數據表（PDF） - Fujitsu

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MB15F76UL
(Rev.:2001)

Dual Serial Input PLL Frequency Synthesizer

Fujitsu 

MB15F76UL

Jun. 2001

Edition 0.2

Table.4 Binary 13-bit Programmable Counter Data Setting

Divide

ratio

(N)

N NN NN NN NN

13 12 11 10 9 8 7 6 5

3

0 00 00 00 00

4

0 00 00 00 00

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

8191

1 11 11 11 11

Note: • Divide ratio less than 3 is prohibited.

Table.5 Binary 5-bit Swallow Counter Data Setting

Divide

ratio

(N)

A AA AA

5 43 21

0

0 00 00

1

0 00 01

⋅

⋅

⋅

⋅

⋅

⋅

31

1 11 11

Note: • Divide ratio (A) range = 0 to 31

Table. 6 Prescaler Data Setting

SW = ”1”

Prescaler

divide ratio

IF-PLL

RF-PLL

4/5

16/17

SW = ”0”

8/9

32/33

Table. 7 Phase Comparator Phase Switching Data Setting

fr > fp

FCIF,RF = 1

FCIF,RF = 0

D oIF,RF

H

L

fr = fp

Z

Z

fr < fp

L

H

VCO Output

Frequency

VCO polarity

1

2

Note: • Z = High–impedance

• Depending upon the VCO and LPF polarity,

FC bit should be set.

NN NN

43 21

00 11

01 00

⋅

⋅

⋅

⋅

11 11

1

2

VCO Input Voltage

10

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