MC100H640FN 查看數據表（PDF） - ON Semiconductor

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MC100H640FN

68030/040 PECL to TTL Clock Driver

ON Semiconductor 

MC10H640, MC100H640

6.2

4.75 V

6.0

5V

5.25 V

5.8

5.6

5.4

5.2

0

25

50

75

85

CLOAD (pF)

Figure 9. tPD versus Load Typical at TA = 25°C

DT

RESET, R

Rtrec

Rtpw

Q0, Q1, Q2, Q3

Q0, Q1

Q4, Q5

Figure 10. MC10H/100H640 Clock Phase and

Reset Recovery Time After Reset Pulse

Din

Q0 → Q3

Q1 → Q2

Q4 & Q5

AFTER POWER UP

OUTPUTS Q4 & Q5 WILL SYNC WITH POSITIVE EDGES OF Din & Q0 → Q3 & NEGATIVE EDGES OF Q0 & Q1

Figure 11. Output Timing Diagram

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