MC100EP35DTR2 查看數據表（PDF） - ON Semiconductor

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MC100EP35DTR2

3.3V / 5VECL JK Flip−Flop

ON Semiconductor 

MC10EP35, MC100EP35

J1

K2

CLK 3

RESET 4

J

K

Flip Flop

R

8 VCC

7Q

6Q

5 VEE

Figure 1. 8−Lead Pinout (Top View) and Logic Diagram

Table 1. PIN DESCRIPTION

PIN

FUNCTION

CLK*

J*, K*

ECL Clock Inputs

ECL Signal Inputs

RESET*

ECL Asynchronous Reset

Q, Q

VCC

VEE

EP

ECL Data Outputs

Positive Supply

Negative Supply

Exposed pad must be connected to a

sufficient thermal conduit. Electrically

connect to the most negative supply or

leave floating open.

* Pins will default LOW when left open.

Table 2. TRUTH TABLE

J

K

RESET CLK

Qn+1

L-

L-

L

L-

H

L

H-

L

L

H-

H

L

X

X

H

Z

Qn

Z

L

Z

H

Z

Qn

X

L

Z = LOW to HIGH Transition

Table 3. ATTRIBUTES

Characteristics

Internal Input Pulldown Resistor

Internal Input Pullup Resistor

ESD Protection

Human Body Model

Machine Model

Charged Device Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

SOIC−8

TSSOP−8

DFN8

Flammability Rating

Transistor Count

Oxygen Index: 28 to 34

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Value

75 kW

N/A

> 4 kV

> 200 V

> 2 kV

Pb Pkg

Level 1

Level 1

Level 1

Pb−Free Pkg

Level 1

Level 3

Level 1

UL−94 V−0 @ 0.125 in

77 Devices

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