MC145502P 查看數據表（PDF） - Motorola => Freescale

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MC145502P

PCM Codec-Filter Mono-Circuit

Motorola => Freescale 

VAG

600 Ω

Rx

5 kΩ

Tx

10 kΩ

681

0.1 µF

MC145503

1 VAG

VDD 16

2

RxO

3 + Tx

15

RDD

RCE 14

4 TxI

RDC 13

5

– Tx

6

Mu/A

12

TDC

11

TDD

7 PDI

TDE 10

8 VSS

VLS 9

51 kΩ*

–5V

* To define RDD when TDD is high Z.

Figure 1. Test Circuit

5V

0.1 µF

ENABLE

CLOCK

Table 1. Options Available by Pin Selection

RSI*

Pin Level

Vref*

Pin Level

Peak–to–Peak Overload Voltage

(Txl, RxO)

VDD

VSS

7.56 V p–p

VDD

VAG + VEXT

(3.02 x VEXT) V p–p

VAG

VSS

5 V p–p

VAG

VAG + VEXT

(2 x VEXT) V p–p

VSS

VSS

6.3 V p–p

VSS

VAG + VEXT

(2.52 x VEXT) V p–p

* On MC145500/03/05, RSI and Vref tied internally to VSS. On MC145501, Vref

tied internally to VSS.

Table 2. Summary of Operation Conditions User Programmed Through Pins VDD, VAG, and VSS

Logic

Level

Pin

Programmed

VDD

Mu/A

Mu–Law Companding Curve and D3/D4 Digital

Formats with Zero Code Suppress

RSI

Peak Overload

Voltage

3.78

VLS

CMOS

Logic Levels

VAG

Mu–Law Companding Curve and Sign

Magnitude Data Format

2.50

TTL Levels

VAG Up

VSS

A–Law Companding Curve and CCITT Digital

Format

3.15

TTL Levels

VSS Up

MC145500•MC145501•MC145502•MC145503•MC145505

12

MOTOROLA

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