MCM6729B 查看數據表（PDF） - Motorola => Freescale
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MCM6729B Datasheet PDF : 7 Pages
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WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
6729B–8
6729B–10
6729B–12
Parameter
Symbol Min Max Min Max Min Max Unit Notes
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Address Valid to End of Write,
G High
tAVAV
8
—
10
—
12
—
ns
3
tAVWL
0
—
0
—
0
—
ns
tAVWH
8
—
9
—
10
—
ns
tAVWH
7
—
8
—
9
—
ns
Write Pulse Width
tWLWH,
8
—
9
—
10
—
ns
tWLEH
Write Pulse Width, G High
tWLWH,
7
—
8
—
9
—
ns
tWLEH
Data Valid to End of Write
tDVWH
4
—
5
—
6
—
ns
Data Hold Time
tWHDX
0
—
0
—
0
—
ns
Write Low to Data High–Z
tWLQZ
—
4
—
5
—
6
ns 4,5,6
Write High to Output Active
tWHQX
3
—
3
—
3
—
ns 4,5,6
Write Recovery Time
tWHAX
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1
tAVAV
tAVWH
tAVWL
HIGH–Z
tWLQZ
tWLEH
tWLWH
tDVWH
DATA VALID
HIGH–Z
tWHAX
tWHDX
tWHQX
MOTOROLA FAST SRAM
MCM6729B
5
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