MICRF219AYQS 查看數據表（PDF） - Micrel

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MICRF219AYQS

300MHz to 450MHz ASK Receiver with RSSI, Auto-Poll, Bit-Check and Squelch

Micrel 

Micrel

MICRF219

REFOSC (MHz)

9.81563

12.15269

13.02519

13.52127

Carrier (MHz)

315.0

390.0

418.0

433.92

HIB Part Number

SA-9.815630-F-10-H-30-30-X

SA-12.152690-F-10-H-30-30-X

SA-13.025190-F-10-H-30-30-X

SA-13.521270-F-10-H-30-30-X

Abracon Part Number

ABLS-9.81563MHz-10J4Y

ABLS-12.15269MHz-10J4Y

ABLS-13.025190MHz-10J4Y

ABLS-13.521270MHz-10J4Y

Table 4. Crystal Frequencies and Vendor Part Numbers

Demodulator Bandwidth Selection and Data

Stream Optimization

JP1 and JP2 are the bandwidth selection for the

demodulator bandwidth. To set it correctly, it is

necessary to know the shortest pulse width of the

encoded data sent in the transmitter. Similar to the

example of the data profile in the Figure 7, PW2 is

shorter than PW1, so PW2 should be used for the

demodulator bandwidth calculation which is found by

0.65/shortest pulse width. After this value is found, the

setting should be done according to Table 5. For

example, if the pulse period is 100µsec, 50% duty

cycle, the pulse width will be 50µsec (PW = (100µsec

× 50%) / 100). Therefore, a bandwidth of 13kHz would

be necessary (0.65 / 50µsec). However, if this data

stream had a pulse period with a 20% duty cycle, then

the bandwidth required would be 32.5kHz (0.65 /

20µsec). This would exceed the maximum bandwidth

of the demodulator circuit. If one tries to exceed the

maximum bandwidth, the pulse would appear

stretched or wider.

SEL0

JP1

Short

Open

Short

Open

SEL1

JP2

Short

Short

Open

Open

Demod.

BW

(hertz)

1625

3250

6500

13000

Shortest

Pulse

(µsec)

400

200

100

50

Maximum

Baud Rate

for 50% Duty

Cycle (Hz)

1250

2500

5000

10000

Table 5. JP1 and JP2 Setting, 433.92MHz

Other frequencies will have different demodulator

bandwidth limits, which is derived from the reference

oscillator frequency. Table 6 and Table 7 shows the

limits for the other two most used frequencies.

SEL0

JP1

Short

Open

Short

Open

SEL1

JP2

Short

Short

Open

Open

Demod.

BW

(hertz)

Shortest

Pulse

(µsec)

1565

416

3130

208

6261

104

12523

52

Maximum

Baud Rate

for 50%

Duty Cycle

(Hz)

1204

2408

4816

9633

Table 6. P1 and JP2 Setting, 418.0MHz

SEL0

JP1

Short

Open

Short

Open

SEL1

JP2

Demod.

BW

(hertz)

Shortest

Pulse

(µsec)

Short

1170

445

Short

2350

223

Open

4700

111

Open

9400

56

Maximum

Baud Rate

for 50%

Duty Cycle

(Hz)

1123

2246

4493

8987

Table 7. JP1 and JP2 Setting, 315MHz

AGC Capacitor and Data Slicer Threshold

Capacitor Selection

Capacitors C6 and C4 are CTH and CAGC capacitors

respectively providing a time base reference for the

data pattern received. These capacitors are selected

according to data profile, pulse duty cycle, dead time

between two received data packets, and if the data

pattern does has or not have a preamble. See Figure

8 for example of a data profile.

June 2011

15

M9999-060811

(408) 944-0800

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