MPC106ARX83TG 查看數據表（PDF） - Motorola => Freescale

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MPC106ARX83TG

PCI Bridge/Memory Controller

Motorola => Freescale 

Pin Assignments

1.5 Pin Assignments

Figure 10 contains the pin assignments for the MPC106, and Figure 11 provides a key to the shading.

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

W

DL26

DL28

DL30

DH31

DH29

DH27

DH25

DH23

DH21

DH19

DH17

DH15

DH13

DH11

DH9

DH7

W

V

DL24

DL27

DL29

DL31

DH30

DH28

DH26

DH24

DH20

DH18

DH16

DH14

DH12

DH10

DH8

DL22

V

MA1/

U

SDBA0/

DL23

AR9

DL25

MA2/

T

SDMA2/

WE

DH0

AR10

MA3/

R

SDMA3/

RCS0

DH2

AR11

MA5/

MA4/

P

SDMA5/ SDMA4/

DH4

AR13

AR12

N

MA6/

SDMA6/

AR14

MA0/

SDBA1/

SDMA0/

AR0

DL17

M

MA8/

SDMA8/

AR16

MA7/

SDMA7/

AR15

RAS0/

CS0

MA9/

L

HRST SDMA9/ QACK

AR17

K

MA11/

MA10/

SDMA11/ SDMA10/

AR19

AR18

RAS3/

CS3

J

MA12/

SDMA12/

AR20

CAS0/

DQM0

PPEN

DL14

DL15

DH1

DH3

DH5

DL18

RAS1/

CS1

RAS2/

CS2

RCS1

H

QREQ

CAS1/

DQM1

SUSPEND

TRST

PLL2

PLL3

DL16

Vss

Vdd

Vss

Vdd

RAS4/

CS4

RAS6/

CS6

Vss

PLL0

DL12

PLL1

DL13

Vss

Vdd

Vdd

Vss

Vss

Vdd

Vdd

Vss

CKO/

DWE2

RAS5/

CS5

RAS7/

CS7

Vdd

MCP

DBGLB/

CKE

DWE1/

DBG3

PIRQ/

SDRAS

DL10

DL11

DL9

DL8

DL7

NC

Vss

AVdd

Vss

NC

DL4

DL3

DL5

DL6

DH22

NC

Vdd

Vss

Vdd

NC

DL2

DL0

DOE/

DBGL2

TOE

DBG1

DH6

DL21

DL20

U

DL1

TV/

BR2

BA0/

BR3

HIT

DIRTY_IN/

BR1

DL19

DCS/

BG3

T

Vss

Vdd

TWE/

BG2

DIRTY_OUT/

BG1

ADS/

DALE/

BRL2

A0

TS

R

Vdd

Vss

Vdd

BA1/

BAA/

BGL2

DWE0/

DBG2

A1

XATS/SDMA

1

P

Vss

Vdd

Vss

LBCLAIM

CI

A2

TA

N

Vdd

Vss

Vdd

WT

GBL

A3

TT4

M

Vss

SYSCLK DBG0

TBST

BR0

A4

TT3

L

Vdd

A9

A8

A7

BG0

A5

TT2

K

Vss

A11

A6

A13

A12

A10

TEA

J

Vdd

Vss

Vdd

A15

A14

A16

TT1

H

G

CAS2/

DQM2

RTC

CAS4/

DQM4

CAS5/

DQM5

Vdd

LSSD_MODE

Vdd

PAR

LOCK

Vss

Vdd

Vss

TSIZ1

TSIZ0

A17

TT0

G

F

BCTL0

BCTL1

CAS6/

DQM6

TCK

Vss

Vdd

Vss

PERR DEVSEL

Vdd

Vss

Vdd

A21

TSIZ2

ARTRY

A18

F

E

CAS3/

DQM3

NMI

CAS7/

DQM7

MDLE/

SDCAS

TDO

Vss

Vdd

SERR

IRDY

Vss

Vdd

A31

A29

A22

A20

A19

E

D

PAR0/

AR1

PAR1/

AR2

TMS

FOE

AD28

AD24

AD21

AD17

AD14

AD10

C/BE0

AD4

AD0

A30

AACK

A23

D

C

PAR2/

AR3

PAR3/

AR4

PAR5/

AR6

AD30

AD26

AD23

AD19

C/BE2

C/BE1

AD12

AD8

AD6

AD2

A27

A25

A24

C

B

PAR4/

AR5

PAR7/

AR8

AD1

TDI

AD7

AD11

AD15

TRDY

AD18

AD22

AD25

AD29

REQ

ISA_MASTER/

BERR

A28

A26

B

A

PAR6/

AR7

GNT

AD3

AD5

AD9

AD13

FRAME

STOP

AD16

AD20

C/BE3

AD27

AD31 FLSHREQ MEMACK

A

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Figure 10. Pin Assignments

NC No Connect

Vss Power Supply Ground

Vdd Power Supply Positive

AVdd Clock Power Supply Positive (K9)

Signals

Figure 11. Pin Assignments Shading Key

VIEW

MPC106 PCI Bridge/Memory Controller Hardware Specifications

15

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