F. Expansion Port Interface
MX98741
TXCLK
ANYACT
JAMO
EDATENL
JAMI
EXTCRS
EDATOE
EDAT
T81
T82
T83
T87
T84
T85
T86
/I/
/J/
/K/
/D1/
T81
T82
T83
/T/
/R/
Figure 8-9 Expansion Port Timing Relationship
Symbol
T81
T82
T83
T84
T85a
T85b
T86
T87
Description
TXCLK rising to ANYACT assert/deassert
TXCLK rising to JAMO assert /deassert
ANYACT assert to EDATENL assert (Note)
TXCLK rising to EDATOE assert
EDAT to TXCLK delay time (Output by MX98741)
EDAT to TXCLK hold time (Input by MX98741)
EDAT to TXCLK setup time (Input by MX98741)
EDATENL asserted to TXCLK rising setup time
MIN.
-
-
-
-
12
4
2
5
MAX.
18
13
17
25
26
-
-
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Note :
If the external arbitor cannot generate EDATENL signals within 35 ns form TXCLK rising edge (or 17 ns after
ANYACT is asserted in figure 9-9) for some reason, EDAT has to be delayed by one TXCLK cycle. Consequently, the
longer the delay time changes the repeater from Class II to Class I. A 7ns PAL is suggested to be used for external
arbitor to minimize the delay.
P/N:PM0342
REV. 1.4, NOV. 07, 1996
31