NB2308AI1HDTG 查看數據表（PDF） - ON Semiconductor
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NB2308AI1HDTG Datasheet PDF : 12 Pages
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NB2308A
Table 7. SWITCHING CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES
Parameter
t1
t1
t3
t4
t5
t6
t7
tJ
tLOCK
Description
Output Frequency
Duty Cycle = (t2 / t1) * 100
(all devices)
Output Rise Time
(−1, −2, −3, −4)
Output Rise Time
(−1H, −5H)
Output Fall Time
(−1, −2, −3, −4)
Output Fall Time
(−1H, −5H)
Output−to−Output Skew on same Bank
(−1, −2, −3, −4)
Output−to−Output Skew
(−1H, −5H)
Output Bank A−to−Output Bank B Skew
(−1, −4, −5H)
Output Bank A−to−Output Bank B Skew
(−2, −3)
Delay, REF Rising Edge to FBK
Rising Edge
Device−to−Device Skew
Cycle−to−Cycle Jitter
(−1, −1H, −4, −5H)
Cycle−to−Cycle Jitter
(−2, −3)
PLL Lock Time
Test Conditions
30 pF load (all devices)
15 pF load (−1H, −5H)
15 pF load (−1, −2, −3, −4)
Measured at 1.4 V, FOUT = < 66.66 MHz
30 pF load
Measured at 1.4 V, FOUT = < 50 MHz
15 pF load
Measured between 0.8 V and 2.0 V
30 pF load
Measured between 0.8 V and 2.0 V
15 pF load
Measured between 0.8 V and 2.0 V
30 pF load
Measured between 2.0 V and 0.8 V
30 pF load
Measured between 0.8 V and 2.0 V
15 pF load
Measured between 2.0 V and 0.8 V
30 pF load
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at VDD/2
Measured at VDD/2 on the FBK pins of the
device
Measured at 66.67 MHz, loaded outputs,
15 pF load
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 133.3 MHz, loaded outputs
15 pF load
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 66.67 MHz, loaded outputs,
15 pF load
Stable power supply, valid clock presented
on REF and FBK pins
Min Typ Max Unit
15
100 MHz
15
133.3
15
133.3
40.0 50.0 60.0 %
45.0 50.0 55.0
2.20 ns
1.50
1.50
2.20 ns
1.50
1.25
200
ps
200
200
400
0
±250 ps
0
700 ps
200
ps
200
100
400
400
1.0 ms
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