SPT7862SIT 查看數據表（PDF） - Signal Processing Technologies
零件编号
产品描述 (功能)
生产厂家
SPT7862SIT Datasheet PDF : 10 Pages
| |||
Figure 1a – Timing Diagram 1
ANALOG IN
CLOCK IN
SAMPLING
CLOCK
(Internal)
DATA OUTPUT
DATA VALID
Figure 1b – Timing Diagram 2
CLOCK IN
1
2
3
4
5
6
7
9
8
10
11
12
13
14
17
15 16
INVALID
tCLK
tC
tCH
tCL
VALID
1 2 3 45
DATA
OUTPUT
Data Ø
tOD
Data 1
DATA VALID
tS
tCH
tS
Table I – Timing Parameters
DESCRIPTION PARAMETERS
Conversion Time
tC
Clock Period
tCLK
Clock High Duty Cycle tCH
Clock Low Duty Cycle tCL
Clock to Output Delay
(30 pF Load)
tOD
Clock to DAV (30 pF load) tS
MIN TYP MAX
tCLK
25
40 50 60
40 50 60
17 20
10 16
UNITS
ns
ns
%
%
ns
ns
Data 2
tCL
Data 3
SPT
4
SPT7862
2/23/00
Share Link: 