AD8608(RevD) 查看數據表（PDF） - Analog Devices

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产品描述 (功能)

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AD8608
(Rev.:RevD)

Precision Low Noise CMOS Rail-to-Rail Input/Output Operational Amplifiers

Analog Devices 

AD8605/AD8606/AD8608

OUTLINE DIMENSIONS

2.90 BSC

1.60 BSC

5

4

2.80 BSC

1

2

3

PIN 1

1.30

1.15

0.90

1.90

BSC

0.95 BSC

0.15 MAX

1.45 MAX 0.22

0.08

0.50 SEATING

0.30 PLANE

10°

5°

0.60

0°

0.45

0.30

COMPLIANT TO JEDEC STANDARDS MO-178AA

Figure 57. 5-Lead Small Outline Transistor Package [SOT-23] (RT-5)

8.75 (0.3445)

8.55 (0.3366)

4.00 (0.1575) 14

3.80 (0.1496) 1

8 6.20 (0.2441)

7 5.80 (0.2283)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

0.10

1.27 (0.0500)

BSC

1.75 (0.0689)

1.35 (0.0531)

0.50 (0.0197) × 45°

0.25 (0.0098)

0.51 (0.0201)

0.31 (0.0122)

SEATING

PLANE

8°

0.25 (0.0098) 0° 1.27 (0.0500)

0.17 (0.0067) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-012AB

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 58. 14-Lead Standard Small Outline Package [SOIC]

Narrow Body (R-14)

3.00

BSC

8

3.00

BSC

5

4.90

BSC

4

PIN 1

0.65 BSC

0.15

1.10 MAX

0.00

0.38

0.22

0.80

0.23

0.08

8°

0°

0.60

0.40

COPLANARITY SEATING

0.10

PLANE

COMPLIANT TO JEDEC STANDARDS MO-187AA

Figure 59. 8-Lead Mini Small Outline Package [MSOP] (RM-8)

5.00 (0.1968)

4.80 (0.1890)

8

4.00 (0.1574)

3.80 (0.1497) 1

5

6.20 (0.2440)

4 5.80 (0.2284)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

1.27 (0.0500)

BSC

1.75 (0.0688)

1.35 (0.0532)

0.50

0.25

(0.0196)

(0.0099)

×

45°

0.51 (0.0201)

SEATING 0.31 (0.0122)

PLANE

8°

0.25 (0.0098) 0° 1.27 (0.0500)

0.17 (0.0067) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-012AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 60. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8)

5.10

5.00

4.90

14

8

4.50

4.40

4.30

1

6.40

BSC

7

PIN 1

1.05

0.65

1.00

BSC

0.80

1.20 0.20

MAX 0.09

0.75

0.15 0.30

0.05 0.19

8°

SEATING

PLANE

0°

COPLANARITY

0.10

0.60

0.45

COMPLIANT TO JEDEC STANDARDS MO-153AB-1

Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)

0.94

0.37

0.90

0.36

0.86

0.35

PIN 1

IDENTIFIER

TOP VIEW

(BALL SIDE DOWN)

1.33

1.29

1.25

0.50 REF

SEATING

PLANE

0.87

0.23

0.18

0.14

BOTTOM VIEW

0.50

0.21

0.17

0.14

0.50

0.20

0.12

Figure 62. 5-Bump 2 × 1 × 2 Array MicroCSP [WLCSP] (CB-5)

Rev. D | Page 18 of 20

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