PALCE20V8V-10JC 查看數據表（PDF） - Advanced Micro Devices

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PALCE20V8V-10JC

EE CMOS 24-Pin Universal Programmable Array Logic

Advanced Micro Devices 

AMD

OE

DQ

CLK

Q

Registered Active Low

OE

DQ

CLK

Q

Registered Active High

Combinatorial I/O Active Low

VCC

Combinatorial I/O Active High

VCC

Note 1

Note 1

Combinatorial Output Active Low

Combinatorial Output Active High

Notes:

1. Feedback is not available on pins 18 (21)

and 19 (23) in the combinatorial output mode.

2. This macrocell configuration is not available on

pins 18 (21) and 19 (23).

Note 2

Adjacent I/O pin

2-160

Dedicated Input

Figure 2. Macrocell Configurations

PALCE20V8 Family

16491D-5

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