H8S/2424 查看數據表（PDF） - Renesas Electronics
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H8S/2424 Datasheet PDF : 1302 Pages
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2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)................. 70
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn..... 71
2.7.5 Absolute Address—@aa:8 /@aa:16 / @aa:24 /@aa:32.......................................... 71
2.7.6 Immediate—#xx:8 / #xx:16/ #xx:32....................................................................... 72
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) ...................................... 72
2.7.8 Memory Indirect—@@aa:8 ................................................................................... 72
2.7.9 Effective Address Calculation ................................................................................ 74
2.8 Processing States.................................................................................................................. 76
2.9 Usage Note........................................................................................................................... 78
2.9.1 Usage Notes on Bit-wise Operation Instructions .................................................... 78
Section 3 MCU Operating Modes .......................................................................79
3.1 Operating Mode Selection ................................................................................................... 79
3.2 Register Descriptions ........................................................................................................... 80
3.2.1 Mode Control Register (MDCR) ............................................................................ 80
3.2.2 System Control Register (SYSCR)......................................................................... 80
3.3 Operating Mode Descriptions .............................................................................................. 82
3.3.1 Mode 1.................................................................................................................... 82
3.3.2 Mode 2.................................................................................................................... 82
3.3.3 Mode 3.................................................................................................................... 82
3.3.4 Mode 4.................................................................................................................... 83
3.3.5 Mode 7.................................................................................................................... 83
3.3.6 Pin Functions .......................................................................................................... 84
3.4 Memory Map in Each Operating Mode ............................................................................... 84
Section 4 Exception Handling ............................................................................. 91
4.1 Exception Handling Types and Priority............................................................................... 91
4.2 Exception Sources and Exception Vector Table .................................................................. 92
4.3 Reset .................................................................................................................................... 94
4.3.1 Reset Exception Handling ...................................................................................... 94
4.3.2 Interrupts after Reset............................................................................................... 96
4.3.3 On-Chip Peripheral Functions after Reset Release................................................. 96
4.4 Trace Exception Handling ................................................................................................... 97
4.5 Interrupt Exception Handling .............................................................................................. 97
4.6 Trap Instruction Exception Handling................................................................................... 98
4.7 Illegal Instruction Exception Handling ................................................................................ 99
4.8 Stack Status after Exception Handling............................................................................... 100
4.9 Usage Note......................................................................................................................... 101
Rev. 1.00 Sep. 19, 2008 Page x of xxviii
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