RT8020E 查看數據表（PDF） - Richtek Technology
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RT8020E Datasheet PDF : 14 Pages
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RT8020E
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD (ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or
discharge COUT, generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing which would indicate a stability
problem.
Thermal Considerations
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, rate of surrounding
airflow, and difference between junction and ambient
temperature. The maximum power dissipation can be
calculated by the following formula :
PD(MAX) = ( TJ(MAX) − TA ) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature and θJA is the junction to ambient
thermal resistance. For recommended operating
conditions specification of the RT8020E DC/DC converter,
TJ(MAX) is the maximum junction temperature of the die
and TA is the ambient temperature. The junction to ambient
thermal resistance θJA is layout dependent. For WDFN-
12L 3x3 packages, the thermal resistance, θJA , is 60°C/
W on a standard JEDEC 51-7 four-layer thermal test board.
The maximum power dissipation at TA = 25°C can be
calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for
WDFN-12L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. For the RT8020E package, the derating
curves in Figure 1 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 1. Derating Curve for RT8020E Package
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of the RT8020E.
` For the main current paths, keep their traces short and
wide.
` Place the input capacitor as close as possible to the
device pins (VIN and GND).
` LX node experiences high frequency voltage swing and
should be kept in a small area. Keep analog components
away from LX node to prevent stray capacitive noise
pick-up.
` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the RT8020E.
` Connect all analog grounds to a command node and
then connect the command node to the power ground
behind the output capacitors.
DS8020E-02 March 2011
www.richtek.com
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