GS74104J-8 查看數據表（PDF） - Giga Semiconductor

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GS74104J-8

1M x 4 4Mb Asynchronous SRAM

Giga Semiconductor 

Block Diagram

Truth Table

CE

OE

H

X

L

L

L

X

L

H

Note: X: “H” or “L”

A0

Row

Decoder

Address

Input

Buffer

A19

CE

WE

OE

Control

Memory Array

Column

Decoder

I/O Buffer

DQ1

DQ4

WE

DQ1 to DQ8

X

Not Selected

H

Read

L

Write

H

High Z

GS74104TP/J

VDD Current

ISB1, ISB2

IDD

Rev: 1.07 1/2001

2/12

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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