S29AL016J70BFN020 查看數據表（PDF） - Spansion Inc.

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S29AL016J70BFN020

16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

Spansion Inc. 

Data Sheet

10.4

Enter/Exit Secured Silicon Sector Command Sequence

The Secured Silicon Sector region provides a secured data area containing a random, sixteen-byte electronic

serial number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle

Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon

Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit

Secured Silicon Sector command sequence returns the device to normal operation. Table 10.1 on page 35

shows the addresses and data requirements for both command sequences. Note that the unlock bypass

mode is not available when the device enters the Secured Silicon Sector. See also Secured Silicon Sector

Flash Memory Region on page 25 for further information.

10.5

Word/Byte Program Command Sequence

The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming

is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles,

followed by the program set-up command. The program address and data are written next, which in turn

initiate the Embedded Program algorithm. The system is not required to provide further controls or timings.

The device automatically generates the program pulses and verifies the programmed cell margin. Table 10.1

on page 35 shows the address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and

addresses are no longer latched. The system can determine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See Write Operation Status on page 36 for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the programming operation. The Byte Program command sequence

should be reinitiated once the device has reset to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from

a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling

algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still

0. Only erase operations can convert a 0 to a 1.

10.6

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program bytes or words to the device faster than using the

standard program command sequence. The unlock bypass command sequence is initiated by first writing two

unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is

required to program in this mode. The first cycle in this sequence contains the unlock bypass program

command, A0h; the second cycle contains the program address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial two unlock cycles required in the standard program

command sequence, resulting in faster total programming time. Table 10.1 on page 35 shows the

requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are

valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command

sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care

for both cycles. The device then returns to reading array data.

Figure 10.1 on page 32 illustrates the algorithm for the program operation. See Erase/Program Operations

on page 47 for parameters, and to Figure 17.5 on page 47 for timing diagrams.

February 18, 2010 S29AL016J_00_10

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