S6B0794 查看數據表（PDF） - Samsung
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S6B0794 Datasheet PDF : 31 Pages
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160 SEG / COM DRIVER FOR STN LCD
SPEC. VER. 3.0 S6B0794
Control input pin for output deselect level
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
. When set to VSS level “L”, the LC drive output pins(Y1-Y160) are set to level
VSS.
DISPOFFB
. While set to “L”, the contents of the shift resister are reset not reading data.
When the DISPOFFB function is canceled, the driver outputs deselect
level(V12 or V43), and the shift data is reading on the falling edge of the LP.
That time, if DISPOFFB removal time can not keep regulation what is shown
AC characteristics (page 25), the shift data is not reading correctly.
AC signal input for LC driving waveform
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
FR
. Normally, input a frame inversion signal.
. The LC driver output pin’s output voltage level can be set using the shift
register output signal and the FR signal.
Table of truth values is shown in Table4.
Mode selection pin
MD
. When set to VSS level “L”, Single mode operation is selected, when set to
VDD level “H”, Dual mode operation is selected.
Dual Mode data input pin
. According to the data shift direction of the data shift register, data can be
DI7
input starting from the 81st bit.
When the chip is used as Dual mode, DI7 will be pull-down.
When the chip is used as Single mode, DI7 won’t be pull-down.
Segment mode/common mode selection pin
S/C
. When set to VSS level ‘L”, common mode is set.
Not used
DI0 – DI6
. Connect DI0 – DI6 to VSS or VDD. Avoiding floating.
XCK
Not used
. XCK is pull-down in common mode, so connect to VSS or open.
LC driver output pins
Y1 – Y160 . Corresponding directly to each bit of the shift register, one level(V0, V12,
V43, or VSS) is selected and output.
Table of truth values is shown in Table4.
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