SAA2505 查看數據表（PDF） - Philips Electronics
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SAA2505 Datasheet PDF : 28 Pages
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Philips Semiconductors
Digital multi-channel audio IC (DUET)
Preliminary specification
SAA2505H
Data sources
I2S-BUS AND EIAJ FORMATTED OUTPUTS
The device has four I2S-bus/EIAJ mode select outputs.
These outputs are capable of outputting data in EIAJ
20, 18 or 16-bit and I2S-bus modes. The EIAJ outputs are
capable of operating in single or double speed, the I2S-bus
output is capable of operating in single, double and quad
speed.
The output ports can either be in the slave or master mode.
In the slave mode they can either be slaved to the I2S-bus
serial clock input (pin 15) or to an external clock. In the
master mode an audio clock is applied to pin 45 that is
256 or 384fs. The master clocking scheme allows the
support of a 96 kHz sample rate DAC by use of the double
speed output option. The quad speed output option is
intended to allow multiple SAA2505H devices to be
connected together.
In order to obtain a high quality digital output in the master
mode the audio clock should be of high quality, having low
jitter and an even mark space ration.
SPDIF FORMATTED OUTPUT
The SPDIF output can transmit either coded data, as
received from the serial data input at pin 56 (SDI0), or
down-mixed 20-bit PCM stereo. The down-mixed stereo
may be Pro-logic encoded.
Together with the PCM samples additional control bits are
transmitted. These are the channel status, user data and
validity bits.
The first five bytes of the channel status bits are user
programmable, all following bytes are zeroed
automatically. Transmission is LSB first.
The user data can carry message lengths of 129 bytes.
These are transmitted over the SPDIF port at a rate of
2 bits per stereo sample. The message buffer of 129 bytes
is loaded via the I2C-bus, if no message is written the
SAA2505H outputs all zeros for the user data.
Table 2 Output port timing information
MODE
Single
Double
Quad
Quad
AUDIO CLOCK
SAMPLING
FREQUENCY
256 or 384fs
256 or 384fs
256fs
384fs
WORD SELECT
SAMPLING
FREQUENCY
1fs
2fs
4fs
4fs
SERIAL CLOCK
SAMPLING
FREQUENCY
64fs
128fs
256fs
192fs
SERIAL DATA BEGIN
SAMPLING
FREQUENCY
−
−
1fs
1fs
Control Inputs
The SAA2505H can be operated in two stand-alone
modes or can be managed by the I2C-bus.
STAND-ALONE MODES
Two stand-alone modes exist to allow the device to be
used in systems without a microcontroller. These two
modes are STANDALONE (pin 1) held HIGH and
STANDALONE connected to RESET (pin 61).
When pin 1 is LOW a reset defaults the outputs to quiet,
however when pin 1 is HIGH a reset defaults the I2S-bus
output to active and the SPDIF output to mute. When pin 1
is HIGH some of the I2C-bus registers cannot be accessed
see Table 3.
I2C-BUS REGISTER CONTROL
The I2C-bus port supports 5 V, 400 kHz operation.
The details of the registers are given in Table 3.
1998 Mar 10
10
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