SC4810BIMLTRT 查看數據表（PDF） - Semtech Corporation

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SC4810BIMLTRT

High Performance Current Mode PWM Controller with Complementary Output, Programmable Delay

Semtech Corporation 

SC4810B/E

POWER MANAGEMENT

Pin Descriptions

Pin # Pin # Pin Name

TSSOP MLPQ

Pin Function

1

15

VDD The power input connection for this device. This pin is shunt regulated at 17.5V which

is sufficiently below the voltage rating of the DMOS output driver stage. VDD should

be bypassed with a 1µF ceramic capacitor.

2

16

LUVLO Line undervoltage lock out pin. An external resistive divider will program the

undervoltage lock out level. During the LUVLO, the Driver OUT1 is disabled and the

softstart is reset. OUT2 continues with a fixed on time of DELAY 1 + DELAY2

approximately.

3

1

SYNC SYNC is a positive edge triggered input with a threshold set to 2.1V. In the Bi-Phase

operation mode the SYNC pin should be connected to the CT (Timing Capacitor) of

the second controller. This will force a out of phase operation. In a single controller

operation, SYNC could be grounded or connected to an external synchronization clock

with a frequency higher than the on-board oscillator frequency. The external OSC

frequency should be 30% greater for guaranteed SYNC operation.

4

2

RCT The oscillator frequency is configured by connecting resistor RT from VREF to RCT

and capacitor CT from RCT to ground. Using the equation below values for RT and

CT can be selected to provide the desired OUT frequency.

where VP-K = RCT peak voltage

F=

1

−

(RT



+ 1k) •

CT

•

ln

1 −

VP−K

VREF



5

3

DMAX Duty cycle up to 95% can be programmed via R18 and R12 (the resistor divider from

Vref in the Application Circuit). When DMAX pin is taken above 3V, 100% duty cycle

is achieved.

6

4

RAMP A resistor from the RAMP to the input voltage and a capacitor from the RAMP to

GND forms the ramp signal of maximum allowable volt-second product. The RAMP is

discharged to GND when OUT1 is low and allowed to charge when OUT1 is high. A

volt-second comparator compares the ramp signal to 3V to limit the maximum

allowable volt-second product: Volt-second product clamp = 3 • Rramp • Cramp.

7

5

DELAY 1 A resistor from these pins to GND programs the non-overlap delay time between

OUT1 and OUT2.

8

6

DELAY 2 A resistor from these pins to GND programs the non-overlap delay time between

OUT2 and OUT1.

 2006 Semtech Corp.

6

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