HC6094 查看數據表（PDF） - Intersil
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HC6094 Datasheet PDF : 9 Pages
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Functional Block Diagram
HC6094
CLK
D0-D13
SCLK
SDI
CS
RST
14
DAC
LATCH
TRANSMITTER
1ST ORDER
1.1MHz LPF
2ND ORDER
1.1MHz LPF
-12 TO 0dB
PGA0
TX O±
SHIFT REGISTER AND LATCHES
RXO+
2ND ORDER
1.1MHz LPF
1ST ORDER
1.1MHz LPF
PGA2
RECEIVER
-9 TO 18dB
PGA1
0 TO 24dB
PGAI± PGAO±
RXI±
Typical Setup
VSSA_TX
D0-D13
CLK
SCLK
SDI
CS
RST
+
RXO±
-
RL = 2000
CTLIN
CTLOUT
14
DAC
1ST ORDER
1.1MHz LPF
-12 TO 0dB
PGA0
2ND ORDER
1.1MHz LPF
+
TX O±
-
RL = 220
SHIFT REGISTER AND LATCHES
VDDD_TX, RX
+5V
VDDA_TX, RX
+5V
VSSA_TX, RX
-5V
GNDD_TX, RX
-9 TO 18dB
PGA2
2ND ORDER
1.1MHz LPF
1ST ORDER
1.1MHz LPF
RECEIVER
PGA IN
GNDA_RX, TX
0 TO 24dB
PGA1
RXI±
PGA OUT
2
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