SPT7863 查看數據表（PDF） - Fairchild Semiconductor
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SPT7863 Datasheet PDF : 11 Pages
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Figure 1A – Timing Diagram 1
1
ANALOG IN
CLOCK IN
3
5
9
7
SAMPLING
CLOCK
(Internal)
DATA OUTPUT
DATA VALID
INVALID
11
13
17
15
VALID
1 2 3 45
Figure 1B – Timing Diagram 2
CLOCK IN
tCLK
tC
tCH
tCL
DATA Data 0
OUTPUT
Data 1
DATA VALID
tOD
tS
tS
tCH
Data 2
tCL
Data 3
Table I – Timing Parameters
DESCRIPTION
PARAMETERS MIN TYP MAX UNITS
Conversion Time
tC
tCLK
ns
Clock Period
tCLK
25
ns
Clock to Output Delay (15 pF Load)
tOD
17
ns
Clock to DAV
tS
10
ns
SPT7863
5
8/21/01
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