SSD1815T1R 查看數據表（PDF） - Solomon Systech

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SSD1815T1R

LCD Segment / Common Driver with Controller for Character Display System

Solomon Systech  

VL6 vs Contrast Settings

-3

0

10

20

30

40

50

60

-5

20

-7

21

22

-9

23

24

-11

25

26

-13

27

-15

contrast level at VDD = 2.775V

Figure 7 - Contrast Curves at Different Interneal Feedback Resistor Ratio Settings

Reset Circuit

This block includes Power On Reset circuitry and the Reset pin,

RES. Both of these having the same reset function. Once RES

receives a negative reset pulse, all internal circuitry will start to initial-

ize. Minimum pulse width for completing the reset sequence is 1us.

The status of the chip after reset is given by:

1. Display is turned OFF

2. 132X64 Display Display Mode with seperated Icon Line

3. Normal segment and display data column address mapping

(SEG0 mapped to address 00h)

4. Read-modify-write mode is OFF

5. Power control register is set to 000b

6. Shift register data clear in serial interface

7. Bias ratio is set to 1/9

8. Static indicator is turned OFF

9. Display start line is set to display RAM column address 0

10. Column address counter is set to 0

11. Page address is set to 0

12. Normal scan direction of the COM outputs

13. Contrast control register is set to 20h

14. Test mode is turned OFF

Display Data Latch

A series of registers carrying the display signal information. For

SSD1815, there are 197 latches (132 + 65) for holding the data,

which will be fed to the HV Buffer Cell and Level Selector to output

the required voltage level.

Level Selector

Level Selector is a control of the display synchronization. Display

voltage can be separated into two sets and used with different cycles.

Synchronization is important since it selects the required LCD voltage

level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD

waveform.

HV Buffer Cell (Level Shifter)

HV Buffer Cell work as a level shifter which translates the low voltage

output signal to the required driving voltage. The output is shifted out

with an internal FRM clock which comes from the Display Timing Gen-

erator. The voltage levels are given by the level selector which is syn-

chronized with the internal M signal.

SSD1815 REV 1.5

12

03/2000

SOLOMON

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