2 Megabit LPC Flash
SST49LF020
Advance Information
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V
Package Power Dissipation Capability (Ta=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Commercial
Ambient Temp
0°C to +85°C
VDD
3.0-3.6V
AC CONDITIONS OF TEST1
Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 25 and 26
1. LPC interface signals use PCI load condition.
TABLE 5: DC OPERATING CHARACTERISTICS (ALL INTERFACES)
Limits
Symbol Parameter
IDD
Power Supply Current
Min
Max
Units
Read
Write
ISB
Standby VDD Current
(LPC Interface)
12
mA
24
mA
100
µA
IRY1
Ready Mode VDD Current
(LPC Interface)
10
mA
II
Input Current for IC Pin
200
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
1
µA
1
µA
VIHI
INIT# Input High Voltage
1.0
VDD+0.5
V
VILI
INIT# Input Low Voltage
-0.5
0.4
V
VIL
Input Low Voltage
-0.5
0.3 VDD
V
VIH
Input High Voltage
0.5 VDD VDD+0.5
V
VOL
Output Low Voltage
VOH
Output High Voltage
0.1 VDD
V
0.9 VDD
V
1. The device is in Ready Mode when no activity is on the LPC bus.
Test Conditions
Address input=VIL/VIH, at f=1/TRC Min,
VDD=VDD Max (PP Mode)
OE#=VIH, WE#=VIH
OE#=VIH, WE#=VIL, VDD=VDD Max (PP Mode)
LFRAME#=VIH, f=33 MHz, CE#=VIH
VDD=VDD Max,
All other inputs ≥ 0.9 VDD or ≤ 0.1 VDD
LFRAME#=VIL, f=33 MHz, VDD=VDD Max
All other inputs ≥ 0.9 VDD or ≤ 0.1 VDD
VIN=GND to VDD, VDD=VDD Max
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Max
VDD=VDD Max
VDD=VDD Min
VDD=VDD Max
IOL=1500 µA, VDD=VDD Min
IOH=-500 µA, VDD=VDD Min
T5.5 526
©2001 Silicon Storage Technology, Inc.
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S71175-02-000 5/01 526