ST8024CDR 查看數據表（PDF） - STMicroelectronics

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ST8024CDR

Smartcard interface

STMicroelectronics 

Electrical characteristics

ST8024

Table 18.

Interrupt output (pin OFF NMOS drain with integrated 20 kΩ pull-up resistor to VDD);

(VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to TA =

25 °C)

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

VOL

Low level output voltage

IOL = 2 mA

0

0.3

V

VOH

High level output voltage IOH = -15 µA

0.75 VDD

V

RPU

Integrated pull-up resistor 20kΩ Pull-up resistor to VDD

16

20

24

kΩ

Table 19.

Symbol

Protection and limitation (VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise

noted. Typical values are to TA = 25 °C)

Parameter

Test conditions

Min. Typ. Max. Unit

|ICC(SD)|

Shutdown and limitation current pin

VCC

II/O(lim)

limitation current pins I/O, AUX1

and AUX2

ICLK(lim) limitation current pin CLK

IRST(lim) limitation current pin RST

TSD Shut down temperature

90

120

mA

-15

15

mA

-70

70

mA

-20

20

mA

150

°C

Table 20.

Symbol

Timing (VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values

are to TA = 25 °C)

Parameter

Test conditions

Min. Typ. Max. Unit

tACT Activation time

(See Figure 5)

tDE Deactivation time

(See Figure 7)

t3

Start of the windows for sending

CLK to card

(See Figure 6)

t5

End of the windows for sending

CLK to card

(See Figure 6)

180

220

µs

60

80

100

µs

130

µs

140

µs

tdebounce

Debounce time pins PRES and

PRES

(See Figure 8)

140

µs

Note: 1 All parameters remain within limits but are tested only statistically for the temperature

range. When a parameter is specified as a function of VDD or VCC it means their actual value

at the moment of measurement.

2 To meet these specifications, pin VCC should be decoupled to CGND using two ceramic

multilayer capacitors of low ESR both with values of 100 nF and 100 nF (see Figure 10).

3 Permitted capacitor values are 100 + 100 nF, or 220 nF.

4 Transition time and duty factor definitions are shown in Figure 3; δ = t1/(t1+ t2).

5 Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2

functions see Table 20

6 Pin PRES is active LOW; pin PRES is active HIGH see Figure 8 and Figure 9; PRES has an

integrated 1.25 µA current source to GND. (PRES to VDD); the card is considered present if

at least one of the inputs PRES or PRES is active.

14/31

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