ST8024CDR 查看數據表（PDF） - STMicroelectronics

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ST8024CDR

Smartcard interface

STMicroelectronics 

Functional description

ST8024

Table 21. Clock frequency selection (1)

CLKDIV1

CLKDIV2

fCLK

0

0

fXTAL/8

0

1

fXTAL/4

1

1

fXTAL/2

1

0

fXTAL

1. The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum

between changes is needed; the minimum duration of any state of CLK is eight periods of XTAL1.

The frequency change is synchronous, which means that during transition no pulse is

shorter than 45 % of the smallest period, and that the first and last clock pulses about the

instant of change have the correct width.

When changing the frequency dynamically, the change is effective for only eight periods of

XTAL1 after the command. The duty factor of fXTAL depends on the signal present at pin

XTAL1. In order to reach a 45 to 55 % duty factor on pin CLK, the input signal on pin XTAL1

should have a duty factor of 48 to 52 % and transition times of less than 5 % of the input

signal period.

If a crystal is used, the duty factor on pin CLK may be 45 to 55 % depending on the circuit

layout and on the crystal characteristics and frequency. In other cases, the duty factor on pin

CLK is guaranteed between 45 and 55 % of the clock period.

The crystal oscillator runs as soon as the IC is powered up. If the crystal oscillator is used,

or if the clock pulse on pin XTAL1 is permanent, the clock pulse is applied to the card as

shown in the activation sequences shown in Figure 5 and Figure 6

If the signal applied to XTAL1 is controlled by the system microcontroller, the clock pulse will

be applied to the card when it is sent by the system microcontroller (after completion of the

activation sequence).

5.4

I/O transceivers

The three data lines I/O, AUX1 and AUX2 are identical.The idle state is realized by both I/O

and I/OUC lines being pulled HIGH via a 11 kΩ resistor (I/O to VCC and I/OUC to VDD). Pin

I/O is referenced to VCC, and pin I/OUC to VDD, thus allowing operation when VCC is not

equal to VDD. The first side of the transceiver to receive a falling edge becomes the master.

An anti-latch circuit disables the detection of falling edges on the line of the other side, which

then becomes a slave. After a time delay td(edge), an N transistor on the slave side is turned

on, thus transmitting the logic 0 present on the master side. When the master side returns to

logic 1, a P transistor on the slave side is turned on during the time delay tpu and then both

sides return to their idle states. This active pull-up feature ensures fast LOW-to-HIGH

transitions; it is able to deliver more than 1 mA at an output voltage of up to 0.9 VCC into an

80 pF load. At the end of the active pull-up pulse, the output voltage depends only on the

internal pull-up resistor and the load current. The current to and from the card I/O lines is

limited internally to 15 mA and the maximum frequency on these lines is 1 MHz.

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