ST8024S 查看數據表（PDF） - Sitronix Technology Co., Ltd.
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ST8024S Datasheet PDF : 27 Pages
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ST8024S
(Segment Mode 3) (LGND=VSS = GND = 0V, VDD = +2.5 to +3.0V, V0 = +15.0 to +30.0V, TOPR = -25 to +85°C)
PARAMETER
SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Shift clock period
tWCK
tR,tF ≤ 10ns
82
ns
1
Shift clock "H" pulse width
tWCKH
28
ns
Shift clock "L” pulse width
tWCKL
28
ns
Data setup time
tDS
20
ns
Data hold time
tDH
23
ns
Latch pulse "H" pulse width
tWLPH
30
ns
Shift clock rise to latch pulse rise time
tLD
0
ns
Shift clock fall to latch pulse fall time
tSL
65
ns
Latch pulse rise to shift clock rise time tLS
30
ns
Latch pulse fall to shift clock fall time
tLH
30
ns
Enable setup time
tS
15
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
/DISPOFF removal time
tSD
100
ns
/DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
Output delay time (2)
Output delay time (3)
tD
tPD1, tPD2
tPD3
CL = 15 pF
CL = 15 pF
CL = 15 pF
57
ns
1.2
µs
1.2
µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
(Common Mode) (LGND=VSS = 0V, VDD = +2.5 to +5.5V, V0 = +15.0 to +30.0V, TOPR = -25 to +85°C)
PARAMETER
SYMBOL CONDITIONS MIN. TYP. MAX.
Shift clock period
tWLP
tR,tF ≤ 20ns
250
Shift clock "H" pulse width
tWLPH
VDD = +5.0± 0.5V
VDD = +2.5+ 4.5V
15
30
Data setup time
tSU
30
Data hold time
tH
50
Input signal rise time
tR
50
Input signal fall time
tF
50
/DISPOFF removal time
tSD
100
/DISPOFF "L" pulse width
tWDL
1.2
Output delay time (1)
tDL
CL = 15 pF
200
Output delay time (2)
tPD1, t PD2
CL = 15 pF
1.2
Output delay time (3)
t PD3
CL = 15 pF
1.2
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
µs
Ver 0.39
Page 18/27
2008/05/05
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