ST802RT1B 查看數據表（PDF） - STMicroelectronics

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ST802RT1B

10/100 real-time Ethernet 3.3 V transceiver

STMicroelectronics 

ST802RT1A, ST802RT1B

Registers and descriptors description

Table 14. RN04 [0d04, 0x04]: Auto-negotiation advertisement register

Bit Bit name

Description

Default

1 -> Next page transfer supported

15 Next Page

0

0 -> Next page transfer not supported

14 RESERVED ---

0

1 -> Advertises that this device has detected a remote fault

13 Remote Fault during auto-negotiation

0

0 -> No remote fault detected.

12 RESERVED ---

0

11

Asymmetric

Pause (full-

duplex)

1 -> Asymmetric pause supported (MAC level)

0 -> No MAC based full-duplex flow control.

0

10

Pause (full- 1 -> Symmetric pause supported (MAC level)

duplex) 0 -> No MAC based full-duplex flow control.

1

9 100BASE-T4 0 -> 100BASE-T4 not supported

0

8

100BASE-TX 1 -> 100BASE-TX Full-duplex is supported by the local device

full duplex 0 -> 100BASE-TX Full-duplex is not supported

Strap

7

100BASE-TX

1 -> 100BASE-TX is supported by the local device

0 -> 100BASE-TX is not supported

Strap

6

10BASE-T full 1 -> 10BASE-T Full-duplex is supported by the local device

duplex 0 -> 10BASE-T Full-duplex is not supported

Strap

5

10BASE-T

1 -> 10BASE-T is supported by the local device

0 -> 10BASE-T is not supported

Strap

4:0 Selector 00001 -> IEEE802.3u

00001b

RW

type

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

Type

-

P

-

-

-

-

-

-

-

-

-

-

Next page: The ST802RT1x supports next page capability.

Reserved: Ignore output when read.

Remote fault: Writing a “1” to bit 13 of the advertisement register causes a remote fault

indicator to be sent to the link partner during auto-negotiation. Writing a “0” to this bit or

resetting the chip clears the remote fault transmission bit. This bit returns the value last

written to it, or else “0” if no write has been completed since the last chip reset.

Asymmetric pause: write '1' if asymmetric pause is supported by MAC when full-duplex link

is available. 1 = Advertise that the DTE (MAC) has implemented both the optional MAC

control sub layer and the pause function as specified in clause 31 and annex 31B of 802.3u.

0 = No MAC based full-duplex flow control.

Pause: The use of this bit is independent of the negotiated data rate, medium, or link

technology. The setting of this bit indicates the availability of additional DTE capability when

full-duplex operation is in use. This bit is used by one MAC to communicate symmetric

pause capability to its link partner, and has no effect on PHY operation.

Advertisement bits: Bits 9:5 of the advertisement register allow the user to customize the

ability information transmitted to the link partner. The default value for each bit reflects the

abilities of the ST802RT1x. By writing a “1” to any of the bits, the corresponding ability is

transmitted to the link partner. Writing a “0” to any bit causes the corresponding ability to be

Doc ID 17049 Rev 1

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